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Renesas RL78/G1H, User Manual

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Renesas RL78/G1H User Manual Download Page 523

RL78/G1H

CHAPTER 15 SERIAL INTERFACE IICA

R01UH0575EJ0120 Rev. 1.20

Page 505 of 920

Dec 22, 2016

The meanings of <7> to <15> in (3) Data ~ data ~ stop condition in Figure 15 - 42 are explained below.

<7> After data transfer is completed, because of ACKEn = 1, the slave device sends an ACK by hardware to the

master device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock.

<8> The master device and slave device set a wait status (SCLAn = 0) at the falling edge of the 9th clock, and both

the master device and slave device issue an interrupt (INTIICAn: end of transfer).

<9> The master device writes the data to transmit to the IICA shift register n (IICAn) and releases the wait status

that it set by the master device.

<10>The slave device reads the received data and releases the wait status (WRELn = 1). The master device then

starts transferring data to the slave device.

<11>When data transfer is complete, the slave device (ACKEn =1) sends an ACK by hardware to the master device.

The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock.

<12>The master device and slave device set a wait status (SCLAn = 0) at the falling edge of the 9th clock, and both

the master device and slave device issue an interrupt (INTIICAn: end of transfer).

<13>The slave device reads the received data and releases the wait status (WRELn = 1).
<14> By the master device setting a stop condition trigger (SPTn = 1), the bus data line is cleared (SDAAn = 0) and

the bus clock line is set (SCLAn = 1). After the stop condition setup time has elapsed, by setting the bus data
line (SDAAn = 1), the stop condition is then generated (i.e. SCLAn =1 changes SDAAn from 0 to 1).

<15> When a stop condition is generated, the slave device detects the stop condition and issues an interrupt

(INTIICAn: stop condition).

Remark 1.

<1> to <15> in Figures 15 - 40 to 15 - 42 represent the entire procedure for communicating data using
the I

2

C bus. Figure 15 - 40 (1) Start condition ~ address ~ data shows the processing from <1> to <6>,

Figure 15 - 41 (2) Address ~ data ~ data shows the processing from <3> to <10>, and Figure 15 - 42 (3)
Data ~ data ~ stop condition shows the processing from <7> to <15>.

Remark 2.

n = 0, 1

Summary of Contents for RL78/G1H

Page 1: ...roducts and product specifications represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest informa...

Page 2: ...range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electroni...

Page 3: ...tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be...

Page 4: ...g of functions Read this manual in the order of the CONTENTS The mark R shows major revised points The revised points can be easily searched by copying an R in the PDF file and specifying it in the Fi...

Page 5: ...may include preliminary versions However preliminary versions are not marked as such Caution The related documents listed above are subject to change without notice Be sure to use the latest version...

Page 6: ...trademark of Renesas Electronics Corporation SuperFlash is a registered trademark of Silicon Storage Technology Inc in several countries including the United States and Japan Other Documents Document...

Page 7: ...port pins 22 3 3 Connection of Unused Pins 23 3 4 Pin Block Diagrams 24 4 CPU ARCHITECTURE 36 4 1 Memory Space 36 4 1 1 Internal program memory space 44 4 1 2 Mirror area 45 4 1 3 Internal data memor...

Page 8: ...er setting examples for used port and alternate functions 89 5 6 Cautions When Using Port Function 95 5 6 1 Cautions on 1 Bit Manipulation Instruction for Port Register n Pn 95 5 6 2 Notes on specifyi...

Page 9: ...3 5 Timer channel enable status register m TEm 160 7 3 6 Timer channel start register m TSm 161 7 3 7 Timer channel stop register m TTm 163 7 3 8 Timer input select register 0 TIS0 164 7 3 9 Timer out...

Page 10: ...oad Register and Counter Rewrite Operation 231 8 4 2 Timer Mode 232 8 4 3 Coordination with Event Link Controller ELC 233 8 5 Cautions for Timer RJ 234 8 5 1 Count Operation Start and Stop Control 234...

Page 11: ...CONTROLLER 267 11 1 Functions of Clock Output Buzzer Output Controller 267 11 2 Configuration of Clock Output Buzzer Output Controller 269 11 3 Registers Controlling Clock Output Buzzer Output Control...

Page 12: ...r Setup Flowchart 312 13 7 1 Setting up software trigger mode 312 13 7 2 Setting up hardware trigger no wait mode 313 13 7 3 Setting up hardware trigger wait mode 314 13 7 4 Setting up test mode 315 1...

Page 13: ...15 3 Registers Controlling Serial Interface IICA 433 15 3 1 Peripheral enable register 0 PER0 434 15 3 2 IICA control register n0 IICCTLn0 434 15 3 3 IICA status register n IICSn 439 15 3 4 IICA flag...

Page 14: ...tivation enable register i DTCENi i 0 to 4 526 16 3 12 DTC base address register DTCBAR 529 16 4 DTC Operation 529 16 4 1 Activation Sources 530 16 4 2 Normal Mode 531 16 4 3 Repeat Mode 532 16 4 4 Ch...

Page 15: ...Notice For Using Baseband Function 704 18 8 1 Notice About Transmission 704 18 8 2 Cautions on First and Second Address Filter Match Monitor Bits 704 19 INTERRUPT FUNCTIONS 705 19 1 Interrupt Function...

Page 16: ...3 4 Operation of Voltage Detector 764 23 4 1 When used as reset mode 764 23 4 2 When used as interrupt mode 766 23 4 3 When used as interrupt and reset mode 768 23 5 Cautions for Voltage Detector 773...

Page 17: ...gramming 818 27 5 1 Self programming procedure 819 27 5 2 Boot swap function 820 27 5 3 Flash shield window function 822 27 6 Security Settings 823 27 7 Data Flash 825 27 7 1 Data flash overview 825 2...

Page 18: ...er supply voltage rising slope characteristics 897 31 7 RF Transceiver Characteristics 898 31 7 1 Recommended operating conditions 898 31 7 2 XIN Frequency Deviation 898 31 7 3 DC characteristics 900...

Page 19: ...P mode of MCU RF operation SLEEP mode POWER_DOWN mode current 0 1 A TYP 3 0 V at STOP mode of MCU RL78 CPU core CISC architecture with 3 stage pipeline Minimum instruction execution time Can be change...

Page 20: ...r modes Normal transfer mode repeat transfer mode block transfer mode Activation sources Activated by interrupt sources Chain transfer function Event link controller ELC Event signals of 13 types can...

Page 21: ...ator true random number complies with AIS31 standard Others On chip BCD binary coded decimal correction circuit ROM RAM capacities Note This is about 47 KB when the self programming function is used F...

Page 22: ...on A Consumer applications TA 40 to 85 C D Industrial applications TA 40 to 85 C Packaging specification 20 Tray 40 Embossed Tape R 5 F 1 1 F L L A x x x N A 2 0 Package type NA HVQFN 0 50 mm pitch RO...

Page 23: ...part numbers refer to the target product page of the Renesas Electronics website Table 1 1 Ordering Part Number List Pin count Package Fields of Application Note Ordering Part Number Code Flash Memor...

Page 24: ...56 57 58 59 60 61 62 63 64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 XOUT REFCLKIN XIN AGNDRF1 RFIP MODE2 VREGO3 VREGO2 GPIO4 ANTSW GPIO3 GPIO2 ANTSELOUT1 GPIO1 ANTSELOUT0 GPIO0 CLKOUT INTOUT P8...

Page 25: ...Port 6 TxD1 TxD3 Transmit Data P70 to P72 P75 to P77 Port 7 VDD Power Supply P80 to P82 Port 8 VSS Ground P100 Port 10 X1 X2 Crystal Oscillator Main System Clock P120 to P124 Port 12 XT1 XT2 Crystal O...

Page 26: ...ANTSELOUT0 GPIO2 ANTSELOUT1 GPIO3 GPIO4 ANTSW VDD VSS VCCRF DDCOUT REGIN VREGOUT1 to VREGOUT3 STANDBY MODE1 MODE2 POR LVD CONTROL POWERONRESET VOLTAGE DETECTOR RESET CONTROL ON CHIP DEBUG SYSTEM CONT...

Page 27: ...r clock 15 kHz TYP RF base clock 48 MHz TYP General purpose register 8 bits 32 registers 8 bits 8 registers 4 banks Minimum instruction execution time 0 03125 s High speed on chip oscillator clock fIH...

Page 28: ...Subsystem clock fSUB 32 768 kHz operation 10 bit resolution A D converter 6 channels Serial interface CSI UART 2 channels CSI 2 channels 1 channel of 2 channels is used for the internal communication...

Page 29: ...I O port of the MCU MCU to RF unit P13 SO20 SIN Serial interface used for internal communication between blocks Since it is dedicated to internal communication MCU output data RF unit input data it ca...

Page 30: ...tween MCU and RF Transceiver Item CSI20 dedicated for internal communication Target channel Channel 0 of serial array unit 1 SAU1 Pins used SCK20 SI20 SO20 pins for communication all on chip dedicated...

Page 31: ...Settings of Unused Internal Pins of MCU After reset release the following internal pins of the MCU need to be set to output mode set the port registers and port mode registers to 0 by software P00 P01...

Page 32: ...4 shows clock resonator connection and Figure 2 1 shows the clock configuration Figure 2 1 Clock Configuration Caution This figure only shows connection between the clock resonator pins and clock line...

Page 33: ...DC converter is output to the DDCOUT pin The power is smoothed by an inductor and capacitor to step down the voltage and then supplied to the REGIN Figure 2 2 shows the power configuration of the RL7...

Page 34: ...racteristics Small loss DC resistance and AC resistance at operational frequency is comfortable L2 L3 L4 Use chip inductance for high frequency Required high Q at 1 GHz band and self resonance is high...

Page 35: ...al frequency is comfortable L5 Use chip inductance for high frequency Required high Q at 1 GHz band and self resonance is higher than 1 GHz VCC 3V L1 C15 C14 C13 64HVQFN XTAL 48MHz C12 C11 C10 C9 C18...

Page 36: ...21 9 P123 8 P124 7 RESETB 6 P40 5 P120 2 P142 1 P143 3 P141 4 P140 10 P137 11 P122 15 VDD 16 P60 30 INTOUT 31 GPIO0 32 GPIO1 29 P82 28 P81 27 P80 26 P70 25 P71 24 P72 23 P75 22 P76 21 P77 20 P31 19 P6...

Page 37: ...pend on the pin The relationship between these power supplies and the pins is shown below Table 3 1 Pin I O Buffer Power Supplies Power Supply Corresponding Pins VDD P02 to P04 P10 to P16 P20 to P22 P...

Page 38: ...P10 Note 3 I O Input port Port 1 7 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting at input port P11 Note 3 P12 Note...

Page 39: ...hibited at reset release Note 1 P120 7 3 3 I O Analog function ANI19 Port 12 1 bit I O port and 4 bit input only port P120 can be set to analog I O For only P120 input output can be specified For only...

Page 40: ...ernal reset pin is not used connect this pin directly or via a resistor to VDD RxD1 RxD3 Input Serial data input pins of serial interface UART1 and UART3 TxD1 TxD3 Output Serial data output pins of se...

Page 41: ...d leave the pins open or set the port s output latch to 1 and independently connect the pins to VDD or VSS via a resistor P70 to P72 P75 to P77 Input Independently connect to VDD or VSS via a resistor...

Page 42: ...lock diagrams are shown in Figures 3 1 to 3 13 Figure 3 1 Pin Block Diagram of Pin Type 1 1 1 Figure 3 2 Pin Block Diagram of Pin Type 2 1 1 Figure 3 3 Pin Block Diagram of Pin Type 2 1 2 Remark Refer...

Page 43: ...e 2 2 1 Remark Refer to 3 1 Port Functions for alternate functions Alternate function Alternate function RD RD Clock generator OSCSEL OSCSELS CMC EXCLK OSCSEL EXCLKS OSCSELS CMC N ch P ch P122 X2 EXCL...

Page 44: ...26 of 920 Dec 22 2016 Figure 3 5 Pin Block Diagram of Pin Type 4 3 3 Internal bus WRPORT RDPORT WRADPC Output latch Pmn ADPC3 to ADPC0 N ch P ch A D converter PM register PMmn WRPM PMS register WRPMS...

Page 45: ...1 3 Remark 1 Refer to 3 1 Port Functions for alternate functions Remark 2 SAU Serial array unit Internal bus Alternate function SAU PM register PMmn PMS register Output latch Pmn Alternate function P...

Page 46: ...Refer to 3 1 Port Functions for alternate functions Remark 2 SAU Serial array unit Internal bus POM register POMmn PM register PMmn PMS register Output latch Pmn Alternate function PU register PUmn W...

Page 47: ...1 Port Functions for alternate functions Remark 2 SAU Serial array unit Internal bus PM register PMmn PU register PUmn PMC register PMCmn Alternate function Output latch Pmn PMS register Alternate fun...

Page 48: ...ions for alternate functions Remark 2 SAU Serial array unit Internal bus PM register PMmn PU register PUmn PMC register PMCmn Alternate function Output latch Pmn PMS register POM register POMmn VDD P...

Page 49: ...er to 3 1 Port Functions for alternate functions Remark 2 SAU Serial array unit Internal bus PU register PUmn PIM register PIMmn Alternate function Output latch Pmn PMS register PM register PMmn Alter...

Page 50: ...rt Functions for alternate functions Remark 2 SAU Serial array unit Internal bus PU register PUmn PIM register PIMmn Alternate function Output latch Pmn PMS register PM register PMmn POM register POMm...

Page 51: ...e functions Remark 2 SAU Serial array unit CMOS TTL Pmn Internal bus PU register PUmn PIM register PIMmn PMC register PMCmn Alternate function Output latch Pmn PMS register PM register PMmn POM regist...

Page 52: ...iagram of Pin Type 12 1 2 Remark 1 Refer to 3 1 Port Functions for alternate functions Remark 2 SAU Serial array unit Internal bus Output latch Pmn Alternate function PMS register Alternate function S...

Page 53: ...920 Dec 22 2016 Figure 3 14 Pin Block Diagram of STANDBY MODE1 MODE2 Figure 3 15 Pin Block Diagram of Pin GPIO0 to GPIO4 Figure 3 16 Pin Block Diagram of Pin INTOUT STANDBY MODE1 MODE2 Input Input ena...

Page 54: ...ER 4 CPU ARCHITECTURE R01UH0575EJ0120 Rev 1 20 Page 36 of 920 Dec 22 2016 CHAPTER 4 CPU ARCHITECTURE 4 1 Memory Space Products in the RL78 G1H can access a 1 MB address space Figures 4 1 to 4 3 show t...

Page 55: ...rity error resets are enabled RPERDIS 0 be sure to initialize RAM areas where data access is to proceed and the RAM area 10 bytes when instructions are fetched from RAM areas respectively Reset signal...

Page 56: ...initialize RAM areas where data access is to proceed and the RAM area 10 bytes when instructions are fetched from RAM areas respectively Reset signal generation sets RAM parity error resets to enabled...

Page 57: ...ip debugging trace function Caution While RAM parity error resets are enabled RPERDIS 0 be sure to initialize RAM areas where data access is to proceed and the RAM area 10 bytes when instructions are...

Page 58: ...AFFFH 2BH 12C00H to 12FFFH 4BH 1AC00H to 1AFFFH 6BH 03000H to 033FFH 0CH 0B000H to 0B3FFH 2CH 13000H to 133FFH 4CH 1B000H to 1B3FFH 6CH 03400H to 037FFH 0DH 0B400H to 0B7FFH 2DH 13400H to 137FFH 4DH 1...

Page 59: ...B3FFH ECH 23400H to 237FFH 8DH 2B400H to 2B7FFH ADH 33400H to 337FFH CDH 3B400H to 3B7FFH EDH 23800H to 23BFFH 8EH 2B800H to 2BBFFH AEH 33800H to 33BFFH CEH 3B800H to 3BBFFH EEH 23C00H to 23FFFH 8FH 2...

Page 60: ...400H to 437FFH 10DH 4B400H to 4B7FFH 12DH 53400H to 537FFH 14DH 5B400H to 5B7FFH 16DH 43800H to 43BFFH 10EH 4B800H to 4BBFFH 12EH 53800H to 53BFFH 14EH 5B800H to 5BBFFH 16EH 43C00H to 43FFFH 10FH 4BC0...

Page 61: ...400H to 637FFH 18DH 6B400H to 6B7FFH 1ADH 73400H to 737FFH 1CDH 7B400H to 7B7FFH 1EDH 63800H to 63BFFH 18EH 6B800H to 6BBFFH 1AEH 73800H to 73BFFH 1CEH 7B800H to 7BBFFH 1EEH 63C00H to 63FFFH 18FH 6BC0...

Page 62: ...so at 01000H to 0107FH For details see CHAPTER 19 INTERRUPT FUNCTIONS 2 CALLT instruction table area The 64 byte area 00080H to 000BFH can store the subroutine entry address of a 2 byte call instructi...

Page 63: ...e mirror area can only be read and no instruction can be fetched from this area The following show examples The PMC register is described below Processor mode control register PMC This register sets t...

Page 64: ...brary R5F11FLL F3F00H to F4309H Caution 4 The internal RAM area in the following products cannot be used as stack memory when using the on chip debugging trace function R5F11FLL F4300H to F46FFH 4 1 4...

Page 65: ...igned for the functions of the special function registers SFR and general purpose registers are available for use Figure 4 5 shows correspondence between data memory and addressing Figure 4 5 Correspo...

Page 66: ...gram status word PSW The program status word is an 8 bit register consisting of various flags set reset by instruction execution Program status word contents are stored in the stack area upon vectored...

Page 67: ...edgeable maskable vectored interrupts Vectored interrupt requests specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers PRn0L PRn0H PRn1L PRn1H PRn2L PRn2H...

Page 68: ...ctions or as a stack area Caution 3 Do not allocate RAM addresses which are used as a stack area a data buffer a branch destination of vector interrupt processing and a DTC transfer destination transf...

Page 69: ...ight 8 bit registers X A C B E D L and H Each register can be used as an 8 bit register and two 8 bit registers can also be used in a pair as a 16 bit register AX BC DE and HL Register banks to be use...

Page 70: ...Configuration of ES and CS Registers Though the data area which can be accessed with 16 bit addresses is the 64 Kbytes from F0000H to FFFFFH using the ES register as well extends this to the 1 Mbyte f...

Page 71: ...manipulation Describe the symbol defined by the assembler for the 16 bit manipulation instruction operand sfrp When specifying an address describe an even address Tables 4 5 to 4 9 give lists of the...

Page 72: ...Port register 12 P12 R W Undefined FFF0DH Port register 13 P13 R W Undefined FFF0EH Port register 14 P14 R W 00H FFF0FH Port register 15 P15 R W 00H FFF14H Serial data register 12 RXD3 SIO30 SDR12 R W...

Page 73: ...gister 0 EGP0 R W 00H FFF39H External interrupt falling edge enable register 0 EGN0 R W 00H FFF3AH External interrupt rising edge enable register 1 EGP1 R W 00H FFF3BH External interrupt falling edge...

Page 74: ...0H FFF94H Hour count register HOUR R W 12H Note FFF95H Week count register WEEK R W 00H FFF96H Day count register DAY R W 01H FFF97H Month count register MONTH R W 01H FFF98H Year count register YEAR...

Page 75: ...ster CRCIN R W 00H FFFD0H Interrupt request flag register 2L IF2L IF2 R W 00H FFFD1H Interrupt request flag register 2H IF2H R W 00H FFFD4H Interrupt mask flag register 2L MK2L MK2 R W FFH FFFD5H Inte...

Page 76: ...equest flag register 1H IF1H R W 00H FFFE4H Interrupt mask flag register 0 MK0L MK0 R W FFH FFFE5H MK0H R W FFH FFFE6H Interrupt mask flag register 1 MK1L MK1 R W FFH FFFE7H MK1H R W FFH FFFE8H Priori...

Page 77: ...scribe the symbol defined by the assembler for the 8 bit manipulation instruction operand addr16 This manipulation can also be specified with an address 16 bit manipulation Describe the symbol defined...

Page 78: ...00H F003CH Pull up resistor option register 12 PU12 R W 00H F003EH Pull up resistor option register 14 PU14 R W 00H F0040H Port input mode register 0 PIM0 R W 00H F0048H Port input mode register 8 PI...

Page 79: ...SSR02L SSR02 R 0000H F0105H F0106H Serial status register 03 SSR03L SSR03 R 0000H F0107H F0108H Serial flag clear trigger register 00 SIR00L SIR00 R W 0000H F0109H F010AH Serial flag clear trigger re...

Page 80: ...R10L SSR10 R 0000H F0141H F0142H Serial status register 11 SSR11L SSR11 R 0000H F0143H F0144H Serial status register 12 SSR12L SSR12 R 0000H F0145H F0146H Serial status register 13 SSR13L SSR13 R 0000...

Page 81: ...clock select register 1 SPS1L SPS1 R W 0000H F0167H F0168H Serial output register 1 SO1 R W 0F0FH F0169H F016AH Serial output enable register 1 SOE1L SOE1 R W 0000H F016BH F0174H Serial output level...

Page 82: ...R W 0000H F01B9H F01BAH Timer output enable register 0 TOE0L TOE0 R W 0000H F01BBH F01BCH Timer output level register 0 TOL0L TOL0 R W 0000H F01BDH F01BEH Timer output mode register 0 TOM0L TOM0 R W...

Page 83: ...l register 00 IICCTL00 R W 00H F0231H IICA control register 01 IICCTL01 R W 00H F0232H IICA low level width setting register 0 IICWL0 R W FFH F0233H IICA high level width setting register 0 IICWH0 R W...

Page 84: ...04 ELSELR04 R W 00H F0307H Event output destination select register 07 ELSELR07 R W 00H F030DH Event output destination select register 13 ELSELR13 R W 00H F0310H Event output destination select regi...

Page 85: ...dition to the function as digital I O ports these ports have several alternate functions For details of the alternate functions see CHAPTER 3 PIN FUNCTIONS The MCU internal pins described below must b...

Page 86: ...M12 PM14 PM15 Port registers P0 to P8 P10 to P15 Pull up resistor option registers PU0 PU1 PU3 PU4 PU7 PU8 PU10 PU12 PU14 Port input mode registers PIM0 PIM8 PIM14 Port output mode registers POM0 POM7...

Page 87: ...d in 1 bit units by pull up resistor option register 1 PU1 This port can also be used for serial interface data I O and clock output Reset signal generation sets port 1 to input mode P10 to P16 pins a...

Page 88: ...6 PM6 The output of the P60 to P63 pins is N ch open drain output 6 V tolerance This port can also be used for serial interface data I O and clock I O Reset signal generation sets port 6 to input por...

Page 89: ...pecified by pull up resistor option register 12 PU12 P121 to P124 are 4 bit input ports To use the P120 pin as a digital I O port set it to digital I O using port mode control register 12 PMC12 This p...

Page 90: ...ort with an output latch Port 15 can be set to the input mode or output mode in 1 bit units using port mode register 15 PM15 This port can also be used for A D converter analog input To use P155 ANI13...

Page 91: ...ontrolling Port Function Port functions are controlled by the following registers Port mode registers PMxx Port registers Pxx Pull up resistor option registers PUxx Port input mode registers PIMxx Por...

Page 92: ...0 PU10 1 PM11 P11 PU11 2 PM12 P12 PU12 3 PM13 P13 PU13 4 PM14 P14 PU14 5 PM15 P15 PU15 6 PM16 P16 PU16 Port 2 0 PM20 P20 1 PM21 P21 2 PM22 P22 Port 3 0 PM30 P30 PU30 1 PM31 P31 PU31 Port 4 0 PM40 P40...

Page 93: ...xx POMxx PMCxx registers and the bits 2 2 Port Bit name PMxx register Pxx register PUxx register PIMxx register POMxx register PMCxx register Port 14 0 PM140 P140 PU140 1 PM141 P141 PU141 2 PM142 P142...

Page 94: ...1 1 PM31 PM30 Note 3 FFF23H FFH R W PM4 PM47 Note 1 PM46 Note 1 PM45 Note 1 PM44 Note 1 PM43 Note 1 PM42 Note 1 PM41 Note 1 PM40 FFF24H FFH R W PM5 PM57 Note 1 PM56 Note 1 PM55 Note 1 PM54 Note 1 PM53...

Page 95: ...Control bits for internal connecting pins After reset release be sure to set to output mode by software set 0 to port mode register Note 3 Control bits for internal connecting pins After reset releas...

Page 96: ...ead in the input mode the pin level is read If it is read in the output mode the output latch value is read Note These registers can be set by a 1 bit or 8 bit memory manipulation instruction Reset si...

Page 97: ...FFF04H 00H output latch R W P5 P57 Note 3 P56 Note 3 P55 Note 3 P54 Note 3 P53 Note 3 P52 Note 3 P51 Note 3 P50 Note 3 FFF05H 00H output latch R W P6 P67 Note 3 P66 Note 3 P65 Note 3 P64 Note 3 P63 P...

Page 98: ...analog function These registers can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears these registers to 00H Only PU4 is set to 01H Figure 5 3 Format of Pull u...

Page 99: ...be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears these registers to 00H Figure 5 4 Format of Port input mode register Caution Be sure to set bits that are not...

Page 100: ...instruction Reset signal generation clears these registers to 00H Caution An on chip pull up resistor is not connected to a bit for which N ch open drain output VDD tolerance mode POMmn 1 is set Figu...

Page 101: ...to FFH Figure 5 6 Format of Port mode control register Caution Be sure to set bits that are not mounted to their initial values Symbol 7 6 5 4 3 2 1 0 Address After reset R W PMC0 1 1 1 1 PMC03 PMC02...

Page 102: ...Set the port to analog input by ADPC register to the input mode by using port mode registers 2 15 PM2 PM15 Caution 2 Do not set the pin set by the ADPC register as digital I O by the analog input cha...

Page 103: ...is cleared when a reset signal is generated 5 4 2 Reading from I O port 1 Output mode The output latch contents are read by a transfer instruction The output latch contents do not change 2 Input mode...

Page 104: ...of CSI10 P03 P04 In case of CSI30 P142 P143 1 Using an external resistor pull up the pin to be used to the power supply of the target device on chip pull up resistor cannot be used 2 Set the correspo...

Page 105: ...on other than SAU Timer RTC clock buzzer output IICA etc is connected to the other input pin of the OR gate When such kind of pins are used by the port function or an alternate function the unused alt...

Page 106: ...in serial output enable register m SOEm which corresponds to the unused output to 0 output disabled and set the SOmn and CKOmn bits in serial output register m SOm to 1 high These are the same settin...

Page 107: ...ing Examples of Registers When Using P02 to P16 Pin Function Pin Name Used Function POMxx PMCxx PMxx Pxx Alternate Function Output Function Name I O SAU Output Function Other than SAU P02 P02 Input 0...

Page 108: ...0 Input ADPC 01H 1 Output ADPC 01H 0 0 1 ANI0 Analog input ADPC 00H 02H to 0FH 00x0xx0x 10x0xx0x 1 AVREFP Reference voltage input ADPC 00H 02H to 0FH 01x0xx0x 1 P21 P21 Input ADPC 01H 02H 1 Output ADP...

Page 109: ...6 V tolerance 0 0 1 SCLA0 0 SCLA0 I O 0 0 P61 P61 Input 1 N ch OD output 6 V tolerance 0 0 1 SDAA0 0 SDAA0 I O 0 0 P62 P62 Input 1 N ch OD output 6 V tolerance 0 0 1 SCLA1 I O 0 0 P63 P63 Input 1 N ch...

Page 110: ...124 Pin Function Pin Name Used Function CMC Pxx Function Name I O EXCLK OSCSEL EXCLKS OSCSELS P121 P121 Input 00xx 10xx 11xx X1 01xx P122 P122 Input 00xx 10xx 11xx X2 01xx EXCLK Input 11xx P123 P123 I...

Page 111: ...AU P130 P130 Output 0 1 P137 P137 Input INTP0 Input P140 P140 Input 1 Output 0 0 1 PCLBUZ0 0 PCLBUZ0 Output 0 0 INTP6 Input 1 P141 P141 Input 1 Output 0 0 1 PCLBUZ1 0 PCLBUZ1 Output 0 0 INTP7 Input 1...

Page 112: ...Examples of Registers When Using P155 and P156 Pin Function Pin Name Used Function ADPC PMxx Pxx Function Name I O P155 P155 Input ADPC 01H to 0EH 1 Output ADPC 01H to 0EH 0 0 1 ANI13 Analog input ADP...

Page 113: ...A 1 bit manipulation instruction is executed in the following order in the RL78 G1H 1 The Pn register is read in 8 bit units 2 The targeted one bit is manipulated 3 The Pn register is written in 8 bit...

Page 114: ...e set to its initial state so as to prevent conflicting outputs For details about the alternate function output see 5 5 Register Settings When Using Alternate Function No specific setting is required...

Page 115: ...be stopped by executing the STOP instruction or setting of the HIOSTOP bit bit 0 of the CSC register The frequency specified by using an option byte can be changed by using the high speed on chip osci...

Page 116: ...WUTMMCK0 of the subsystem clock supply mode control register OSMC or both are set to 1 However if WDTON 1 WUTMMCK0 0 and bit 0 WDSTBYON of the option byte 000C0H is 0 the low speed on chip oscillator...

Page 117: ...ystem clock control register CKC Clock operation status control register CSC Oscillation stabilization time counter status register OSTC Oscillation stabilization time select register OSTS Peripheral...

Page 118: ...Real time clock 12 bit interval timer Controller Controller Timer RJ Timer array unit 0 Serial array unit 0 Serial interface IICA1 Serial interface IICA0 A D converter Serial array unit 1 DTC Timer R...

Page 119: ...er CMC System clock control register CKC Clock operation status control register CSC Oscillation stabilization time counter status register OSTC Oscillation stabilization time select register OSTS Per...

Page 120: ...tion stabilization time of fXT counting on the software Caution 6 Although the maximum system clock frequency is 32 MHz the maximum frequency of the X1 oscillator is 20 MHz Cautions and Remark are giv...

Page 121: ...power consumption oscillation AMPHS1 AMPHS0 1 0 is selected Configure the circuit of the circuit board using material with little parasitic capacitance and wiring resistance Place a ground pattern tha...

Page 122: ...clock 12 bit interval timer clock output buzzer output and watchdog timer is also changed at the same time Consequently stop each peripheral function when changing the CPU peripheral hardware clock C...

Page 123: ...Caution 4 When starting XT1 oscillation by setting the XSTOP bit wait for oscillation of the subsystem clock to stabilize by setting a wait time using software Caution 5 Do not stop the clock selected...

Page 124: ...f reset signal the STOP instruction and MSTOP bit 7 of clock operation status control register CSC 1 clear the OSTC register to 00H Remark The oscillation stabilization time counter starts counting in...

Page 125: ...e X1 clock oscillating Note therefore that only the status up to the oscillation stabilization time set by the OSTS register is set to the OSTC register after the STOP mode is released Caution 3 The X...

Page 126: ...PU clock from the high speed on chip oscillator clock or the subsystem clock to the X1 clock and when using the high speed on chip oscillator clock for switching the X1 clock from the oscillating stat...

Page 127: ...sed as the CPU clock When the STOP mode is entered and then released while the high speed on chip oscillator clock is being used as the CPU clock with the X1 clock oscillating Note therefore that only...

Page 128: ...interface IICA0 Serial array unit 1 Serial array unit 0 Timer array unit 1 Timer array unit 0 DTC Timer RJ The PER0 and PER1 registers can be set by a 1 bit or 8 bit memory manipulation instruction R...

Page 129: ...1 Enables input clock supply SFR used by the A D converter can be read and written IICA0EN Control of serial interface IICA0 input clock supply 0 Stops input clock supply SFR used by the serial inter...

Page 130: ...rray unit 1 input clock supply 0 Stops input clock supply SFR used by timer array unit 1 cannot be written Timer array unit 1 is in the reset status 1 Enables input clock supply SFR used by timer arra...

Page 131: ...6 5 4 3 2 1 0 PER1 0 0 0 0 DTCEN 0 0 TRJ0EN DTCEN Control of DTC input clock supply 0 Stops input clock supply DTC cannot run 1 Enables input clock supply DTC can run TRJ0EN Control of timer RJ0 input...

Page 132: ...ontrol register OSMC Address F00F3H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 OSMC RTCLPC 0 0 WUTMMCK0 0 0 0 0 RTCLPC Setting in STOP mode or HALT mode while subsystem clock is selected as CPU clock...

Page 133: ...d as the CPU peripheral hardware clock fCLK Caution 3 After the frequency is changed with the HOCODIV register the frequency is switched after the following transition time has elapsed Operation for u...

Page 134: ...ent must be executed regularly or before the frequency accuracy is required Figure 6 13 Format of High speed on chip oscillator trimming register HIOTRM Note The value after reset is the value adjuste...

Page 135: ...cillator Figure 6 14 Example of External Circuit of X1 Oscillator Cautions are listed on the next page 6 4 2 XT1 oscillator The XT1 oscillator oscillates with a crystal resonator 32 768 kHz TYP connec...

Page 136: ...ltra low power consumption oscillation AMPHS1 AMPHS0 1 0 as the mode of the XT1 oscillator evaluate the resonators Make the wiring between the XT1 and XT2 pins and the resonators as short as possible...

Page 137: ...d X2 pins and the resonators in a multi layer board or double sided board Do not configure a layout that will cause capacitance elements and affect the oscillation characteristics Remark When using th...

Page 138: ...of X2 may increase with XT1 resulting in malfunctioning Remark When using the subsystem clock replace X1 and X2 with XT1 and XT2 respectively Also insert resistors in series on the XT2 side e Wiring n...

Page 139: ...tomatically starts oscillating after reset release 6 4 4 Low speed on chip oscillator The low speed on chip oscillator clock is used only as the watchdog timer real time clock 12 bit interval timer an...

Page 140: ...IN High speed system clock fMX X1 clock fX External main system clock fEX High speed on chip oscillator clock fIH Subsystem clock fSUB XT1 clock fXT External subsystem clock fEXS Low speed on chip osc...

Page 141: ...r the clock oscillation to stabilize and then set switching via software see 6 6 2 Example of setting X1 oscillation clock and 6 6 3 Example of setting XT1 oscillation clock Note 1 The internal reset...

Page 142: ...ed on chip oscillator frequency select register HOCODIV Option byte setting Address 000C2H Option byte 000C2H 7 6 5 4 3 2 1 0 1 CMODE0 0 1 1 0 FRQSEL3 0 1 FRQSEL2 0 1 FRQSEL1 0 1 FRQSEL0 0 1 CMODE0 Fl...

Page 143: ...7 6 5 4 3 2 1 0 HOCODIV 0 0 0 0 0 HOCODIV2 HOCODIV1 HOCODIV0 HOCODIV2 HOCODIV1 HOCODIV0 Selection of high speed on chip oscillator clock frequency FRQSEL3 0 FRQSEL3 1 0 0 0 fIH 24 MHz fIH 32 MHz 0 0...

Page 144: ...or the cases where the fx is equal to or more than 10 MHz in such cases set 1 the AMPH bit to operate the X1 oscillator 2 Using the OSTS register select the oscillation stabilization time of the X1 os...

Page 145: ...perable voltage range of the flash operation mode set in the option byte 000C2H before and after the clock change Value of option byte 000C2H Flash operation mode Operating frequency range Operating v...

Page 146: ...al time clock and 12 bit interval timer on the subsystem clock for ultra low current consumption in the STOP mode or HALT mode during CPU operation on the subsystem clock 2 Set 1 the OSCSELS bit of th...

Page 147: ...X1 oscillation EXCLK input Stops XT1 oscillation EXCLKS input Oscillatable High speed on chip oscillator Operating X1 oscillation EXCLK input Stops XT1 oscillation EXCLKS input Oscillatable High speed...

Page 148: ...APTER 31 ELECTRICAL SPECIFICATIONS 3 CPU operating with subsystem clock D after reset release A The CPU operates with the high speed on chip oscillator clock immediately after a reset release B Note T...

Page 149: ...bit memory manipulation instruction after reset release This setting is not necessary if it has already been set Remark 1 Don t care Remark 2 A to J in Tables 6 3 to 6 7 correspond to A to J in Figure...

Page 150: ...illation accuracy stabilization time changes according to the temperature conditions and the STOP mode period Setting sequence of SFR registers Setting Flag of SFR Register CSC Register Oscillation ac...

Page 151: ...be set see CHAPTER 31 ELECTRICAL SPECIFICATIONS 10 HALT mode E set while CPU is operating with high speed on chip oscillator clock B HALT mode F set while CPU is operating with high speed system cloc...

Page 152: ...CPU changing from STOP mode H to SNOOZE mode J For details about the setting for switching from the STOP mode to the SNOOZE mode see 13 8 SNOOZE Mode Function 14 5 7 Calculating transfer clock frequen...

Page 153: ...lation of high speed on chip oscillator HIOSTOP 0 After elapse of oscillation stabilization time After checking that the CPU clock is switched to the clock after change X1 oscillation can be stopped M...

Page 154: ...Enabling input of external clock from the EXCLK pin and selection of high speed system clock as main system clock OSCSEL 1 EXCLK 1 MSTOP 0 MCS 1 External subsystem clock Transition not possible Exter...

Page 155: ...register When the CPU clock is switched the peripheral hardware clock is also switched Remark 1 The number of clocks listed in Tables 6 11 and 6 12 is the number of CPU clocks before switchover Remar...

Page 156: ...able 6 13 Conditions Before the Clock Oscillation Is Stopped and Flag Settings Clock Conditions Before Clock Oscillation Is Stopped External Clock Input Disabled Flag Settings of SFR Register High spe...

Page 157: ...1 as two 8 bit timers higher and lower The functions that can use channels 1 and 3 as 8 bit timers are as follows Interval timer upper or lower 8 bit timer square wave output lower 8 bit timer only Ex...

Page 158: ...the timer input pin TImn has reached a specific value 4 Input pulse interval measurement Counting is started by the valid edge of a pulse signal input to a timer input pin TImn The count value of the...

Page 159: ...s a set to generate a pulse with a specified period and a specified duty factor Remark m Unit number m 0 1 n Channel number n 0 to 3 p q Slave channel number n p q 3 7 1 3 8 bit timer operation functi...

Page 160: ...ster mn TCRmn Register Timer data register mn TDRmn Timer input TI03 Timer output TO03 Control registers Registers of unit setting block Peripheral enable register 0 PER0 Timer clock select register m...

Page 161: ...r Timer clock select register 0 TPS0 fCLK 21 fCLK 22 fCLK 24 fCLK 26 fCLK 20 to fCLK 215 PRS031PRS030PRS021PRS020PRS013PRS012PRS011PRS010PRS003PRS002PRS001PRS000 2 2 4 4 Selector Selector Selector Sel...

Page 162: ...S01 TIS00 Timer input select register 0 TIS0 Event input from ELC Interrupt signal to slave channel Noise filter TNFEN00 Noise filter enable register 1 NFEN1 Mode selection Timer controller INTTM01H T...

Page 163: ...n Count clock selection CKS021 Interrupt signal to slave channel Interrupt signal from master channel Slave master controller Mode selection Timer controller INTTM03H Timer interrupt Interrupt control...

Page 164: ...a count clock Whether the counter is incremented or decremented depends on the operation mode that is selected by the MDmn3 to MDmn0 bits of timer mode register mn TMRmn refer to 7 3 3 Timer mode regi...

Page 165: ...tatus Note This indicates the value read from the TCRmn register when channel n has stopped operating as a timer TEmn 0 and has been enabled to operate as a counter TSmn 1 The read value is held in th...

Page 166: ...TDRmn n 1 3 i When timer data register mn TDRmn is used as compare register Counting down is started from the value set to the TDRmn register When the count value reaches 0000H an interrupt signal INT...

Page 167: ...mode register mn TMRmn Timer status register mn TSRmn Timer channel enable status register m TEm Timer channel start register m TSm Timer channel stop register m TTm Timer input select register 0 TIS0...

Page 168: ...to their initial values and writing to them is ignored except for the timer input select register 0 TIS0 noise filter enable register 1 NFEN1 port mode register 3 PM3 and port register 3 P3 Timer sta...

Page 169: ...g of the TPSm register during timer operation is possible only in the following cases If the PRSm00 to PRSm03 bits can be rewritten n 0 to 3 All channels for which CKm0 is selected as the operation cl...

Page 170: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPSm 0 0 PRSm 31 PRSm 30 0 0 PRSm 21 PRSm 20 PRSm 13 PRSm 12 PRSm 11 PRSm 10 PRSm 03 PRSm 02 PRSm 01 PRSm 00 PRS mk3 PRS mk2 PRS mk1 PRS mk0 Selection of operation...

Page 171: ...n Be sure to clear bits 15 14 11 10 to 0 Remark 1 fCLK CPU peripheral hardware clock frequency Remark 2 For details of a signal of fCLK 2r selected with the TPSm register see 7 5 1 Count clock fTCLK A...

Page 172: ...counter one count or capture and one count Rewriting the TMRmn register is prohibited when the register is in operation when TEmn 1 However bits 7 and 6 CISmn1 CISmn0 can be rewritten even while the...

Page 173: ...TS mn1 STS mn0 CIS mn1 CIS mn0 0 0 MD mn3 MD mn2 MD mn1 MD mn0 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMRmn n 0 CKS mn1 CKS mn0 0 CCS mn 0 Note STS mn2 STS mn1 STS mn0 CIS mn1 CIS mn0 0 0 MD mn3...

Page 174: ...dependent channel operation function or as slave channel in simultaneous channel operation function 1 Operates as master channel in simultaneous channel operation function Only the channel 2 can be se...

Page 175: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMRmn n 1 3 CKS mn1 CKS mn0 0 CCS mn SPLIT mn STS mn2 STS mn1 STS mn0 CIS mn1 CIS mn0 0 0 MD mn3 MD mn2 MD mn1 MD mn0 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMR...

Page 176: ...ation of TCR 0 0 0 Interval timer mode Interval timer Square wave output Divider function PWM output master Counting down 0 1 0 Capture mode Input pulse interval measurement Counting up 0 1 1 Event co...

Page 177: ...er mn TSRmn Remark m Unit number m 0 1 n Channel number n 0 to 3 Remark The OVF bit does not change immediately after the counter has overflowed but changes upon the subsequent capture Address F01A0H...

Page 178: ...ignal generation clears this register to 0000H Figure 7 17 Format of Timer channel enable status register m TEm Remark m Unit number m 0 1 n Channel number n 0 to 3 Address F01B0H F01B1H TE0 F01F0H F0...

Page 179: ...0 0 0 0 TSm3 TSm2 TSm1 TSm0 TSH m3 Trigger to enable operation start operation of the higher 8 bit timer when channel 3 is in the 8 bit timer mode 0 No trigger operation 1 The TEHm3 bit is set to 1 a...

Page 180: ...t does the following wait period is required from when timer mode register mn TMRmn is set until the TSmn TSHm1 TSHm3 bit is set to 1 When the TImn pin noise filter is enabled TNFENmn 1 Four cycles of...

Page 181: ...ear bits 15 to 12 10 8 to 4 of the TTm register to 0 Remark 1 When the TTm register is read 0 is always read Remark 2 m Unit number m 0 1 n Channel number n 0 to 3 Address F01B4H F01B5H TT0 F01F4H F01...

Page 182: ...r input to be selected Thus the TIS02 bit cannot be set to 1 when fSUB is selected as fCLK CSS in CKC register 1 Caution 2 When selecting an event input signal from the ELC using timer input select re...

Page 183: ...ipulation instruction with TOEmL Reset signal generation clears this register to 0000H Figure 7 21 Format of Timer output enable register m TOEm Caution Be sure to clear bits 15 to 4 2 to 0 to 0 in TO...

Page 184: ...3 TO03 pin as a port function pin set the corresponding TOmn bit to 0 The TOm register can be set by a 16 bit memory manipulation instruction The lower 8 bits of the TOm register can be set with an 8...

Page 185: ...t with an 8 bit memory manipulation instruction with TOLmL Reset signal generation clears this register to 0000H Figure 7 23 Format of Timer output level register m TOLm Caution Be sure to clear bits...

Page 186: ...mory manipulation instruction with TOMmL Reset signal generation clears this register to 0000H Figure 7 24 Format of Timer output mode register m TOMm Caution Be sure to clear bits 15 to 4 2 to 0 to 0...

Page 187: ...is enabled after synchronization with the operating clock fMCK for the target channel whether the signal keeps the same value for two clock cycles is detected When the noise filter is OFF only synchro...

Page 188: ...1 0 0 0 0 TNFEN03 0 TNFEN01 TNFEN00 TNFEN03 Enable disable using noise filter of TI03 pin input signal 0 Noise filter OFF 1 Noise filter ON TNFEN01 Enable disable using noise filter of input signal se...

Page 189: ...Using port pins for the timer array unit functions requires setting of the registers that control the port functions multiplexed on the target pins port mode register PMxx port register Pxx and port m...

Page 190: ...slave channel that operates in combination with the master channel must be the same value as that of the master channel 7 A master channel can transmit INTTMmn interrupt start software trigger and co...

Page 191: ...aneous channel operation function in 7 4 1 Basic rules of simultaneous channel operation function do not apply to the channel groups Remark m Unit number m 0 1 n Channel number n 0 to 3 Channel group...

Page 192: ...s selected according to the CKSmn1 and CKSmn0 bits of the lower bit TMRmn register 6 For the higher 8 bits the TSHm1 TSHm3 bit is manipulated to start channel operation and the TTHm1 TTHm3 bit is mani...

Page 193: ...Smn 0 The count clock fTCLK is between fCLK to fCLK 215 by setting of timer clock select register m TPSm When a divided fCLK is selected however the clock selected in TPSmn register but a signal which...

Page 194: ...venience Figure 7 27 Timing of fCLK and count clock fTCLK When CCSmn 1 noise filter unused 1 Setting TSmn bit to 1 enables the timer to be started and to become wait state for valid edge of input sign...

Page 195: ...performs count down operation see 7 5 3 2 Operation of event counter mode Capture mode No operation is carried out from start trigger detection until count clock generation The first count clock load...

Page 196: ...starts in the interval timer mode 5 When the TCRmn register counts down and its count value is 0000H INTTMmn is generated and the value of timer data register mn TDRmn is loaded to the TCRmn register...

Page 197: ...TCRmn register value is counted down according to the count clock of the valid edge of the TImn input Figure 7 29 Operation Timing In Event Counter Mode Remark The timing is shown in Figure 7 29 indic...

Page 198: ...If a clock has been input to TImn the trigger exists when capturing starts counting starts when a trigger is detected even if no edge is detected Therefore the first captured value 4 does not determin...

Page 199: ...lue is 0000H INTTMmn is generated and the value of the TCRmn register becomes FFFFH and counting stops Figure 7 31 Operation Timing In One count Mode Remark The timing is shown in Figure 7 31 indicate...

Page 200: ...n input the value of the TCRmn register is captured to timer data register mn TDRmn and INTTMmn is generated Figure 7 32 Operation Timing In Capture One count Mode High level Width Measurement Remark...

Page 201: ...TMmn set signal is masked 3 While timer output is enabled TOEmn 1 INTTMmn master channel timer interrupt and INTTMmp slave channel timer interrupt are transmitted to the TOm register Writing to the TO...

Page 202: ...e timer output signal is set to the initial status by setting timer output register m TOm 3 The timer output operation is enabled by writing 1 to the TOEmn bit writing to the TOm register is disabled...

Page 203: ...register m TOLm does not affect the timer operation the values can be changed during timer operation To output an expected waveform from the TOmn pin by timer operation however set the TOm TOEm TOLm a...

Page 204: ...setting of timer output level register m TOLm is invalid when master channel output mode TOMmn 0 When the timer operation starts after setting the default level the toggle signal is generated and the...

Page 205: ...at PWM Output TOMmn 1 Remark 1 Set The output signal of the TOmp pin changes from inactive level to active level Reset The output signal of the TOmp pin changes from active level to inactive level Re...

Page 206: ...egister Has Been Changed during Timer Operation Remark 1 Set The output signal of the TOmn pin changes from inactive level to active level Reset The output signal of the TOmn pin changes from active l...

Page 207: ...0 n Channel number n 3 n 0 2 for master channel p Slave channel number p 3 fTCLK Internal reset signal Internal reset signal INTTMmp Internal reset signal INTTMmn TOmp pin TOmp TOmn pin TOmn Toggle To...

Page 208: ...he TOmn bit of all the channels can be manipulated collectively Only the desired bits can also be manipulated by enabling writing only to the TOmn bits TOEmn 0 that correspond to the relevant bits of...

Page 209: ...controlled Figure 7 39 shows operation examples when the interval timer mode TOEmn 1 TOMmn 0 is set Figure 7 39 Operation examples of timer interrupt at count operation start and TOmn output a When M...

Page 210: ...clock fMCK for channel n whether the signal keeps the same value for two clock cycles is detected The following shows differences in waveforms output from the noise filter between when the noise filt...

Page 211: ...ng to the timer input pin 1 Noise filter is disabled When bits 12 CCSmn 9 STSmn1 and 8 STSmn0 in the timer mode register mn TMRmn are 0 and then one of them is set to 1 wait for at least two cycles of...

Page 212: ...he first count clock after the channel start trigger bit TSmn TSHm1 TSHm3 of timer channel start register m TSm is set to 1 If the MDmn0 bit of timer mode register mn TMRmn is 0 at this time INTTMmn i...

Page 213: ...Remark 1 m Unit number m 0 1 n Channel number n 0 to 3 Remark 2 TSmn Bit n of timer channel start register m TSm TEmn Bit n of timer channel enable status register m TEm TCRmn Timer count register mn...

Page 214: ...output when counting is started Selection of TImn pin input edge 00B Sets 00B because these are not used Start trigger selection 000B Selects only software start Setting of MASTERmn bit channel 2 0 In...

Page 215: ...mode and the port register is 0 TOmn does not change because channel stops operating The TOmn pin outputs the TOmn set level Operation is resumed Operation start Sets the TOEmn bit to 1 only if using...

Page 216: ...he TOmn pin output level Clears the TOmn bit to 0 after the value to be held is set to the port register When holding the TOmn pin output level is not necessary Setting not required The TOmn pin outpu...

Page 217: ...Sm to 1 The TCRmn register counts down each time the valid input edge of the TImn pin has been detected When TCRmn 0000H the TCRmn register loads the value of the TDRmn register again and outputs INTT...

Page 218: ...emark 1 m Unit number m 0 n Channel number n 3 Remark 2 TSmn Bit n of timer channel start register m TSm TEmn Bit n of timer channel enable status register m TEm TImn TImn pin input signal TCRmn Timer...

Page 219: ...ion of TImn pin input edge 00B Detects falling edge 01B Detects rising edge 10B Detects both edges 11B Setting prohibited Start trigger selection 000B Selects only software start Setting of MASTERmn b...

Page 220: ...and some power is consumed Operation is resumed Operation start Sets the TSmn bit to 1 The TSmn bit automatically returns to 0 because it is a trigger bit TEmn 1 and count operation starts Value of t...

Page 221: ...lows at this time the OVF bit of timer status register mn TSRmn is set to 1 If the counter does not overflow the OVF bit is cleared After that the above operation is repeated As soon as the count valu...

Page 222: ...0 Remark 1 m Unit number m 0 n Channel number n 3 Remark 2 TSmn Bit n of timer channel start register m TSm TEmn Bit n of timer channel enable status register m TEm TImn TImn pin input signal TCRmn Ti...

Page 223: ...ting is started Selection of TImn pin input edge 00B Detects falling edge 01B Detects rising edge 10B Detects both edges 11B Setting prohibited Capture trigger selection 001B Selects the TImn pin inpu...

Page 224: ...1 and count operation starts Timer count register mn TCRmn is cleared to 0000H When the MDmn0 bit of the TMRmn register is 1 INTTMmn is generated During operation Set values of only the CISmn1 and CI...

Page 225: ...th is to be measured is detected later the count value is transferred to timer data register mn TDRmn and at the same time INTTMmn is output If the counter overflows at this time the OVF bit of timer...

Page 226: ...umber m 0 n Channel number n 3 Remark 2 TSmn Bit n of timer channel start register m TSm TEmn Bit n of timer channel enable status register m TEm TImn TImn pin input signal TCRmn Timer count register...

Page 227: ...mn when counting is started Selection of TImn pin input edge 10B Both edges to measure low level width 11B Both edges to measure high level width Start trigger selection 010B Selects the TImn pin inpu...

Page 228: ...to 0 because it is a trigger bit TEmn 1 and the TImn pin start edge detection wait status is set Detects the TImn pin input count start valid edge Clears timer count register mn TCRmn to 0000H and st...

Page 229: ...atus is set Timer count register mn TCRmn starts operating upon TImn pin input valid edge detection and loads the value of timer data register mn TDRmn The TCRmn register counts down from the value of...

Page 230: ...as Delay Counter Remark 1 m Unit number m 0 n Channel number n 3 Remark 2 TSmn Bit n of timer channel start register m TSm TEmn Bit n of timer channel enable status register m TEm TImn TImn pin input...

Page 231: ...Detects falling edge 01B Detects rising edge 10B Detects both edges 11B Setting prohibited Start trigger selection 001B Selects the TImn pin input valid edge Setting of MASTERmn bit channel 2 0 Indep...

Page 232: ...ration is resumed Operation start Sets the TSmn bit to 1 The TSmn bit automatically returns to 0 because it is a trigger bit TEmn 1 and the start trigger detection the valid edge of the TImn pin input...

Page 233: ...er the TCRmp register loads the value of the TDRmp register and the counter counts down to 0000H When the counter reaches 0000H it outputs INTTMmp and waits until the next start trigger INTTMmn from t...

Page 234: ...terrupt controller Interrupt signal INTTMmn Timer data register mn TDRmn Operation clock CKm0 CKm1 Timer counter register mn TCRmn TSmn Interrupt controller Interrupt signal INTTMmp Timer data registe...

Page 235: ...er p 3 Remark 2 TSmn TSmp Bit n p of timer channel start register m TSm TEmn TEmp Bit n p of timer channel enable status register m TEm TCRmn TCRmp Timer count registers mn mp TCRmn TCRmp TDRmn TDRmp...

Page 236: ...0 MDmn3 0 MDmn2 0 MDmn1 0 MDmn0 1 Operation mode of channel n 000B Interval timer Setting of operation when counting is started 1 Generates INTTMmn when counting is started Selection of TImn pin inpu...

Page 237: ...ne count mode Start trigger during operation 1 Trigger input is valid Selection of TImp pin input edge 00B Sets 00B because these are not used Start trigger selection 100B Selects INTTMmn of master ch...

Page 238: ...ets timer mode registers mn mp TMRmn TMRmp of two channels to be used determines operation mode of channels An interval period value is set to timer data register mn TDRmn of the master channel and a...

Page 239: ...TDRmn register is loaded to the TCRmn register and the counter starts counting down again At the slave channel the value of the TDRmp register is loaded to the TCRmp register triggered by INTTMmn of t...

Page 240: ...When Using Timer Array Unit 7 10 1 Cautions When Using Timer output Depends on products a pin is assigned a timer output and other alternate functions In this case outputs of the other alternate funct...

Page 241: ...cessed by accessing the TRJ0 register Table 8 1 lists the Timer RJ Specifications Figure 8 1 shows the Timer RJ Block Diagram Table 8 1 Timer RJ Specifications Item Description Operating modes Timer m...

Page 242: ...ystem clock supply mode control register OSMC to 1 However fIL cannot be selected as the count source for timer RJ when fSUB is selected as the count source for the real time clock or the 12 bit inter...

Page 243: ...r CPU processing For this reason if this wait state occurs the number of instruction execution clocks is increased by the number of wait clocks The number of wait clocks for access to the TRJ0 registe...

Page 244: ...uction Reset signal generation clears this register to 00H Figure 8 2 Format of Peripheral enable register 1 PER1 Caution 1 When setting timer RJ be sure to set the TRJ0EN bit to 1 first If TRJ0EN 0 w...

Page 245: ...Subsystem clock supply mode control register OSMC Address F00F3H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 OSMC RTCLPC 0 0 WUTMMCK0 0 0 0 0 WUTMMCK0 Selection of operation clock fRTC for real time c...

Page 246: ...to FFFFH Note 2 When the setting of bits TCK2 to TCK0 in the TRJMR0 register is other than 001B fCLK 8 or 011B fCLK 2 if the TRJ0 register is set to 0000H a request signal to the DTC and the ELC is g...

Page 247: ...0 is written to this bit by a program Condition for setting to 1 When the counter underflows TSTOP Timer RJ count forced stop Note 1 When 1 is written to this bit the count is forcibly stopped The re...

Page 248: ...register are set to 0 count stops Note 2 When selecting fIL as the count source set the WUTMMCK0 bit in the subsystem clock supply mode control register OSMC to 1 However fIL cannot be selected as the...

Page 249: ...d register in synchronization with the count source and then to the counter in synchronization with the next count source Figure 8 7 shows the Timing of Rewrite Operation with TSTART Bit Value Figure...

Page 250: ...aches 0000H and the next count source is input an underflow occurs and an interrupt request is generated Figure 8 8 shows the Operation Example in Timer Mode Figure 8 8 Operation Example in Timer Mode...

Page 251: ...tion in event counter mode The ELC setting procedure is shown below Procedure for starting operation 1 Set the event output destination select register ELSELRn for the ELC 2 Set the operating mode for...

Page 252: ...After 0 count stops is written to the TSTART bit during a count operation the TCSTF bit remains 1 for two cycles of the CPU clock When the TCSTF bit is set to 0 the count is stopped Do not access the...

Page 253: ...ers Registers TRJ0 TRJCR0 and TRJMR0 8 5 6 When Count is Forcibly Stopped by TSTOP Bit After the counter is forcibly stopped by the TSTOP bit in the TRJCR0 register do not access the following SFRs fo...

Page 254: ...hen the low speed oscillation clock fIL 15kHz is selected only the constant period interrupt function is available However the constant period interrupt interval when fIL is selected will be calculate...

Page 255: ...rcuit Buffer Buffer Buffer Buffer Buffer Second count register SEC 7 bit Minute count register MIN 7 bit Hour count register HOUR 6 bit Day count register DAY 6 bit Week count register WEEK 3 bit Inte...

Page 256: ...ystem clock supply mode control register OSMC Real time clock control register 0 RTCC0 Real time clock control register 1 RTCC1 Second count register SEC Minute count register MIN Hour count register...

Page 257: ...register 3 PM3 port register 3 P3 Real time clock control register 0 RTCC0 Real time clock control register 1 RTCC1 Second count register SEC Minute count register MIN Hour count register HOUR Day co...

Page 258: ...al time clock When the low speed oscillation clock fIL 15 kHz is selected only the constant period interrupt function is available The constant period interrupt interval when fIL is selected will be c...

Page 259: ...setting the RWAIT bit bit 0 of real time clock control register 1 RTCC1 to 1 If the AMPM bit value is changed the values of the hour count register HOUR change according to the specified time system T...

Page 260: ...and WALIE 1 rewrite the WALE bit after disabling interrupt servicing INTRTC by using the interrupt mask flag register Furthermore clear the WAFG and RTCIF flags after rewriting the WALE bit When setti...

Page 261: ...t the same time which interrupt occurred can be judged by checking the fixed cycle interrupt status flag RIFG and the alarm detection status flag WAFG upon INTRTC occurrence Remark 2 The internal coun...

Page 262: ...ter SEC is written 9 3 6 Minute count register MIN The MIN register is an 8 bit register that takes a value of 0 to 59 decimal and indicates the count value of minutes It counts up when the second cou...

Page 263: ...ime system specified using bit 3 AMPM of real time clock control register 0 RTCC0 If the AMPM bit value is changed the values of the HOUR register change according to the specified time system The HOU...

Page 264: ...0 for AM and 1 for PM Table 9 2 Displayed Time Digits 24 Hour Display AMPM 1 12 Hour Display AMPM 0 Time HOUR Register Time HOUR Register 0 00 H 12 a m 12 H 1 01 H 1 a m 01 H 2 02 H 2 a m 02 H 3 03 H...

Page 265: ...buffer and then to the counter up to two cycles of fRTC later Even if the hour count register overflows while this register is being written this register ignores the overflow and is set to the value...

Page 266: ...ry manipulation instruction Reset signal generation clears this register to 00H Figure 9 11 Format of Week count register WEEK Caution 1 The value corresponding to the month count register MONTH or th...

Page 267: ...e clock 9 3 11 Year count register YEAR The YEAR register is an 8 bit register that takes a value of 0 to 99 decimal and indicates the count value of years It counts up when the month count register M...

Page 268: ...1 0 SUBCUD DEV F6 F5 F4 F3 F2 F1 F0 DEV Setting of watch error correction timing 0 Corrects watch error when the second digits are at 00 20 or 40 every 20 seconds 1 Corrects watch error only when the...

Page 269: ...s register is 00H if the AMPM bit is set to 1 after reset Caution Set a decimal value of 00 to 23 01 to 12 or 21 to 32 to this register in BCD code If a value outside the range is set the alarm is not...

Page 270: ...day Hour Hour Minute Minute Hour Hour Minute Minute 10 1 10 1 10 1 10 1 W W W W W W W W W W W W W W 0 1 2 3 4 5 6 Every day 0 00 a m 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 Every day 1 30 a m 1 1 1 1 1 1 1 0 1...

Page 271: ...arting operation when shifting to HALT STOP mode without waiting for INTRTC 1 after RTCE 1 End Setting MIN RTCE 0 Setting WUTMMCK0 Start Setting HOUR Setting SEC INTRTC 1 Stops counter operation Sets...

Page 272: ...the RWST bit to become 1 after setting the RTCE bit to 1 and then setting the RWAIT bit to 1 Afterward setting the RWAIT bit to 0 and shifting to HALT STOP mode after checking again by polling that t...

Page 273: ...r SEC minute count register MIN hour count register HOUR week count register WEEK day count register DAY month count register MONTH and year count register YEAR may be read in any sequence All the reg...

Page 274: ...d RTCIF flags after rewriting the MIN register Remark The second count register SEC minute count register MIN hour count register HOUR week count register WEEK day count register DAY month count regis...

Page 275: ...use the same interrupt source INTRTC When using these two types of interrupts at the same time which interrupt occurred can be judged by checking the fixed cycle interrupt status flag RIFG and the ala...

Page 276: ...68 60 3 When DEV 1 Correction value Note Number of correction counts in 1 minute Oscillation frequency Target frequency 1 32768 60 Note The correction value is the watch error correction value calcula...

Page 277: ...31 2 ppm is 63 1 ppm or lower The expression for calculating the correction value when DEV is 0 is applied Correction value Number of correction counts in 1 minute 3 Oscillation frequency target frequ...

Page 278: ...n when DEV F6 F5 F4 F3 F2 F1 F0 0 0 1 0 1 1 0 0 Internal counter 16 bit count value SEC 00 01 40 19 20 39 59 00 Count start 0000H 7FFFH 56H 86 8054H 8055H 0000H 0001H 7FFFH 0000H 0001H 7FFFH 0000H 805...

Page 279: ...timer includes the following hardware Figure 10 1 Block Diagram of 12 bit Interval Timer Table 10 1 Configuration of 12 bit Interval Timer Item Configuration Counter 12 bit counter Control registers P...

Page 280: ...et the RTCEN bit to 1 and then set the following register while oscillation of the count clock is stable If RTCEN 0 writing to the control register controlling the 12 bit interval timer is ignored and...

Page 281: ...er to 00H Figure 10 3 Format of Subsystem clock supply mode control register OSMC Address F00F3H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 OSMC RTCLPC 0 0 WUTMMCK0 0 0 0 0 WUTMMCK0 Selection of opera...

Page 282: ...and entering standby mode again confirm that the written value of the RINTE bit is reflected or wait that more than one clock of the count clock has elapsed after returned from standby mode Then enter...

Page 283: ...he value specified for the ITCMP11 to ITCMP0 bits the 12 bit counter value is cleared to 0 counting continues and an interrupt request signal INTIT is generated at the same time The basic operation of...

Page 284: ...enter HALT or STOP mode see Example 1 in Figure 10 6 After setting RINTE to 1 wait for at least one cycle of the count clock and then enter HALT or STOP mode see Example 2 in Figure 10 6 Figure 10 6...

Page 285: ...ut is a function to output a square wave of buzzer frequency One pin can be used to output a clock or buzzer sound The PCLBUZn pin outputs a clock selected by clock output select register n CKSn Figur...

Page 286: ...ock buzzer controller fMAIN fSUB PCLOE0 0 0 0 PCLOE0 5 3 Internal bus CSEL0 CCS02 CCS01 CCS00 Output latch P141 PM141 PM140 PCLOE1 0 0 0 CSEL1 CCS12 CCS11 CCS10 Prescaler 8 Internal bus Clock buzzer c...

Page 287: ...sters n CKSn These registers set output enable disable for clock output or for the buzzer frequency output pin PCLBUZn and set the output clock Select the clock to be output from the PCLBUZn pin by us...

Page 288: ...ark 1 n 0 1 Remark 2 fMAIN Main system clock frequency fSUB Subsystem clock frequency Address FFFA5H CKS0 FFFA6H CKS1 After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CKSn PCLOEn 0 0 0 CSELn CCSn2 CCSn1 CCS...

Page 289: ...t pin port mode register PMxx port register Pxx For details see 5 3 1 Port mode registers PMxx and 5 3 2 Port registers Pxx Specifically using a port pin with a multiplexed clock or buzzer output func...

Page 290: ...he clock output select register CKSn of the PCLBUZn pin output in disabled status 3 Set bit 7 PCLOEn of the CKSn register to 1 to enable clock buzzer output Remark 1 The controller used for outputting...

Page 291: ...r is set by the option byte 000C0H Program loop is detected in the following cases If the watchdog timer counter overflows If a 1 bit manipulation instruction is executed on the watchdog timer enable...

Page 292: ...ting of Watchdog Timer Option Byte 000C0H Watchdog timer interval interrupt Bit 7 WDTINT Window open period Bits 6 and 5 WINDOW1 WINDOW0 Controlling counter operation of watchdog timer Bit 4 WDTON Ove...

Page 293: ...register WDTE Note The WDTE register reset value differs depending on the WDTON bit setting value of the option byte 000C0H To operate watchdog timer set the WDTON bit to 1 Caution 1 If a value other...

Page 294: ...r that write the WDTE register the second time or later after a reset release during the window open period If the WDTE register is written during a window close period an internal reset signal is gen...

Page 295: ...llation clock and when the watchdog timer is to be cleared after the STOP mode release by an interval interrupt 12 4 2 Setting overflow time of watchdog timer Set the overflow time of the watchdog tim...

Page 296: ...r writing ACH to WDTE must proceed outside the corresponding period from among those listed below over which clearing of the counter is prohibited for example confirming that the interval timer interr...

Page 297: ...d between the STOP mode release and the watchdog timer overflow is short an overflow occurs during the oscillation stabilization time causing a reset Consequently set the overflow time in consideratio...

Page 298: ...lues and 10 bit or 8 bit resolution can be selected by the ADTYP bit of the A D converter mode register 2 ADM2 The A D converter has the following function 10 bit or 8 bit resolution A D conversion 10...

Page 299: ...lected channel once Sequential conversion mode A D conversion is sequentially performed on the selected channels until it is stopped by software Operation voltage mode Standard 1 or standard 2 mode Co...

Page 300: ...n register ADS A D converter mode register 1 ADM1 6 5 3 ADTMD1 ADTMD0 ADSCM ADTRS1 ADTRS0 A D converter mode register 2 ADM2 ADREFPM ADREFP0 V SS A D voltage comparator Successive approximation regist...

Page 301: ...on the most significant bit MSB of the successive approximation register SAR is set If the analog input voltage is less than the reference voltage 1 2 AVREF the MSB bit of the SAR is reset After that...

Page 302: ...ter ADCRH The A D conversion result is loaded from the successive approximation register to this register each time A D conversion is completed and the ADCRH register stores the higher 8 bits of the A...

Page 303: ...erter mode register 1 ADM1 A D converter mode register 2 ADM2 10 bit A D conversion result register ADCR 8 bit A D conversion result register ADCRH Analog input channel specification register ADS Conv...

Page 304: ...registers are cleared to their initial values and writing to them is ignored except for port mode registers 2 12 and 15 PM2 PM12 PM15 port mode control register 12 PMC12 and A D port configuration re...

Page 305: ...e first conversion result Otherwise ignore data of the first conversion Caution 1 Change the FR2 to FR0 LV1 and LV0 bits while conversion is stopped ADCS 0 ADCE 0 Caution 2 Do not set the ADCS bit to...

Page 306: ...One shot conversion mode When 0 is written to ADCS Hardware trigger wait mode Select mode Sequential conversion mode When a hardware trigger is input When 0 is written to ADCS One shot conversion mod...

Page 307: ...no wait mode the ADCS flag is not automatically cleared to 0 when A D conversion ends Instead 1 is retained Caution 3 Only rewrite the value of the ADCE bit when ADCS 0 while in the conversion stopped...

Page 308: ...e Conversion Clock fAD Number of Conversion Clock Note Conversion Time Conversion Time at 10 Bit Resolution 2 7 V VDD 3 6 V FR2 FR1 FR0 LV1 LV0 fCLK 1 MHz fCLK 4 MHz fCLK 8 MHz fCLK 16 MHz fCLK 32 MHz...

Page 309: ...de Register 0 ADM0 Mode Conversion Clock fAD Number of Conversion Clock Note 4 Conversion Time Conversion Time at 10 Bit Resolution 1 8 V VDD 3 6 V Note 1 Note 2 Note 3 FR2 FR1 FR0 LV1 LV0 fCLK 1 MHz...

Page 310: ...hen there is A D power supply stabilization wait time Normal mode 1 2 hardware trigger wait mode Note 1 A D Converter Mode Register 0 ADM0 Mode Conversion Clock fAD Number of A D Power Supply Stabiliz...

Page 311: ...n Time Selection 4 4 4 When there is A D power supply stabilization wait time Low voltage mode 1 2 hardware trigger wait mode Note 1 A D Converter Mode Register 0 ADM0 Mode Conversion Clock fAD Number...

Page 312: ...re 13 5 A D Converter Sampling and A D Conversion Timing Example for Software Trigger Mode ADCS Conversion time Conversion time Sampling timing INTAD Successive conversion Conversion start Sampling Sa...

Page 313: ...ck conversion start time A D power supply stabilization wait time A D conversion time Caution 3 In modes other than SNOOZE mode input of the next INTRTC or INTIT will not be recognized as a valid hard...

Page 314: ...e conversion is stopped ADCS 0 ADCE 0 Caution 2 When using AVREFP and AVREFM specify ANI0 and ANI1 as the analog input channels and specify input mode by using the port mode register Address F0010H Af...

Page 315: ...sion is performed without operating the CPU the SNOOZE mode The SNOOZE mode function can only be specified when the high speed on chip oscillator clock is selected for the CPU peripheral hardware cloc...

Page 316: ...register Caution 2 When the ADCR register is accessed in 16 bit units the higher 10 bits of the conversion result are read in order starting at bit 15 13 3 6 8 bit A D conversion result register ADCR...

Page 317: ...o not set the pin that is set by the A D port configuration register ADPC as digital I O by the ADS register Caution 4 Do not set the pin that is set by Port mode control register 12 PMC12 as digital...

Page 318: ...per limit setting register ADUL 13 3 9 Conversion result comparison lower limit setting register ADLL This register is used to specify the setting for checking the lower limit of the A D conversion re...

Page 319: ...ement select the side reference voltage as the target for conversion The ADTES register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 00H Figur...

Page 320: ...tion register ADPC For details see 5 3 1 Port mode registers PMxx 5 3 6 Port mode control registers PMCxx and 5 3 7 A D port configuration register ADPC When using the ANI0 to ANI2 ANI13 and ANI14 pin...

Page 321: ...register is manipulated as follows Sampled voltage Voltage tap Bit 8 1 Sampled voltage Voltage tap Bit 8 0 6 Comparison is continued in this way up to bit 0 of the SAR register 7 Upon completion of t...

Page 322: ...0 ADM0 to 0 Writing to the analog input channel specification register ADS during A D conversion interrupts the current conversion after which A D conversion of the analog input specified by the ADS r...

Page 323: ...tage ADCR A D conversion result register ADCR value SAR Successive approximation register Figure 13 17 shows the Relationship Between Analog Input Voltage and A D Conversion Result Figure 13 17 Relati...

Page 324: ...D conversion is performed on the analog input respecified by the ADS register The partially converted data is discarded 6 Even if a hardware trigger is input during conversion operation A D conversion...

Page 325: ...ed 7 When ADCS is cleared to 0 during conversion operation the current A D conversion is interrupted and the system enters the A D conversion standby status 8 When ADCE is cleared to 0 while in the A...

Page 326: ...nversion operation the current A D conversion is interrupted and conversion restarts The partially converted data is discarded 8 When ADCS is cleared to 0 during conversion operation the current A D c...

Page 327: ...rtially converted data is discarded 8 When ADCS is overwritten with 1 during conversion operation the current A D conversion is interrupted and conversion restarts at the first channel The partially c...

Page 328: ...rwritten with 1 during conversion operation the current A D conversion is interrupted and conversion restarts The partially converted data is discarded 7 When ADCS is cleared to 0 during conversion op...

Page 329: ...on the current A D conversion is interrupted the system enters the hardware trigger standby status and the A D converter enters the stop status When ADCE 0 inputting a hardware trigger is ignored and...

Page 330: ...hese are used to select the reference voltage ADRCK bit This is used to select the range for the A D conversion result comparison value generated by the interrupt signal from AREA1 AREA3 and AREA2 ADT...

Page 331: ...the A D conversion result comparison value generated by the interrupt signal from AREA1 AREA3 and AREA2 ADTYP bit 8 bit 10 bit resolution ADUL ADLL register These are used to specify the upper limit...

Page 332: ...ts These are used to select the reference voltage ADRCK bit This is used to select the range for the A D conversion result comparison value generated by the interrupt signal from AREA1 AREA3 and AREA2...

Page 333: ...setting ADM0 register FR2 to FR0 LV1 and LV0 bits These are used to specify the A D conversion time ADM1 register ADTMD1 and ADTMD0 bits These are used to specify the software trigger mode ADSCM bit T...

Page 334: ...before switching to the STOP mode For details about these settings see 13 7 3 Setting up hardware trigger wait mode Note 2 At this time bit 2 AWC of A D converter mode register 2 ADM2 is set to 1 Afte...

Page 335: ...ase of the A D converter mode register 2 ADM2 If the AWC bit is left set to 1 A D conversion will not start normally in the subsequent SNOOZE or normal operation mode 2 If no interrupt is generated af...

Page 336: ...es ADS register ADS4 to ADS0 bits These are used to select the analog input channels ADM0 register setting ADM1 register setting ADM2 register setting ADUL ADLL register setting ADS register setting T...

Page 337: ...itten to the ADCR or ADCRH registers 2 Conflict between the ADCR or ADCRH register write and the A D converter mode register 0 ADM0 write the analog input channel specification register ADS or A D por...

Page 338: ...lengthen the sampling time or connect a larger capacitor with a value of about 0 1 F to the pin from among ANI0 to ANI2 ANI13 ANI14 and ANI19 to which the source is connected see Figure 13 30 The samp...

Page 339: ...emoving the first conversion result 9 A D conversion result register ADCR ADCRH read operation When a write operation is performed to A D converter mode register 0 ADM0 analog input channel specificat...

Page 340: ...resistance and capacitance values shown in Table 13 7 are not guaranteed values 11 Starting the A D converter Start the A D converter after the AVREFP and VDD voltages stabilize Table 13 7 Resistance...

Page 341: ...and RF transceiver For this channel only the master can be selected Remark In this chapter indexes m n p and q are used for the unit number channel number CSI number and UART number respectively Each...

Page 342: ...data SI For details about the settings see 14 5 Operation of 3 Wire Serial I O CSIp Communication Data transmission reception Data length of 7 or 8 bits Phase control of transmit receive data MSB LSB...

Page 343: ...arty Full duplex UART communication can be performed by using a channel dedicated to transmission even numbered channel and a channel dedicated to reception odd numbered channel For details about the...

Page 344: ...data input SI10 SI20 SI21 SI30 pins for 3 wire serial I O RxD1 RxD3 pins for UART Serial data output SO10 SO20 SO21 SO30 pins for 3 wire serial I O TxD1 TxD3 pins for UART Control registers Registers...

Page 345: ...LC 021 DLS 020 TSF 02 OVF 02 BFF 02 PEF 02 Serial status register 02 SSR02 Communication status Clear Communication controller Mode selection UART1 for reception CK01 CK00 Prescaler CK01 CK00 SNFEN 10...

Page 346: ...or Edge level detection Mode selection UART3 for reception Edge level detection Noise elimination enabled disabled SNFEN30 0 SOL12 0 SOL10 Error controller Error controller Serial output register 1 SO...

Page 347: ...in the lower 8 bits When data is to be transmitted set transmit data to be transferred to the shift register to the lower 8 bits The data stored in the lower 8 bits of this register is as follows depe...

Page 348: ...lear bit 8 to 0 Remark For the function of the higher 7 bits of the SDRmn register see 14 3 Registers Controlling Serial Array Unit Address FFF44H FFF45H SDR02 FFF46H FFF47H SDR03 After reset 0000H R...

Page 349: ...r mn SMRmn Serial communication operation setting register mn SCRmn Serial data register mn SDRmn Serial flag clear trigger register mn SIRmn Serial status register mn SSRmn Serial channel start regis...

Page 350: ...ignored and even if the register is read only the default value is read except for noise filter enable register 0 NFEN0 port input mode registers port output mode registers port mode registers port m...

Page 351: ...ommonly supplied to each channel CKm1 is selected by bits 7 to 4 of the SPSm register and CKm0 is selected by bits 3 to 0 Rewriting the SPSm register is prohibited when the register is in operation wh...

Page 352: ...MHz fCLK 5 MHz fCLK 10 MHz fCLK 20 MHz fCLK 32 MHz 0 0 0 0 fCLK 2 MHz 5 MHz 10 MHz 20 MHz 32 MHz 0 0 0 1 fCLK 2 1 MHz 2 5 MHz 5 MHz 10 MHz 16 MHz 0 0 1 0 fCLK 22 500 kHz 1 25 MHz 2 5 MHz 5 MHz 8 MHz...

Page 353: ...F0117H SMR03 After reset 0020H R W F0150H F0151H SMR10 to F0156H F0157H SMR13 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMRmn CKS mn CCS mn 0 0 0 0 0 STS mn Note 0 SIS mn0 Note 1 0 0 0 MD mn1 MD m...

Page 354: ...bit memory manipulation instruction Reset signal generation sets the SCRmn register to 0087H Address F0114H F0115H SMR02 F0116H F0117H SMR03 After reset 0020H R W F0150H F0151H SMR10 to F0156H F0157H...

Page 355: ...EOC mn PTC mn1 PTC mn0 DIR mn 0 SLC mn1 Note 1 SLC mn0 0 1 1 DLS mn0 TXE mn RXE mn Setting of operation mode of channel n 0 0 Disable communication 0 1 Reception only 1 0 Transmission only 1 1 Transmi...

Page 356: ...ves without parity 0 1 Outputs 0 parity Note 2 No parity judgment 1 0 Outputs even parity Judged as even parity 1 1 Outputs odd parity Judges as odd parity Be sure to set PTCmn1 PTCmn0 0 0 in the CSI...

Page 357: ...lower 8 bits The SDRmn register can be read or written in 16 bit units However the higher 7 bits can be written or read only when the operation is stopped SEmn 0 During operation SEmn 1 a value is wri...

Page 358: ...set signal generation clears the SIRmn register to 0000H Figure 14 11 Format of Serial flag clear trigger register mn SIRmn Note The SIR03 and SIR13 registers only Caution Be sure to clear bits 15 to...

Page 359: ...n 0 Communication is stopped or suspended 1 Communication is in progress Clear conditions The STmn bit of the STm register is set to 1 communication is stopped or the SSmn bit of the SSm register is s...

Page 360: ...n to the FECTmn bit of the SIRmn register Set condition A stop bit is not detected when UART reception ends PEF mn Parity error detection flag of channel n 0 No error occurs 1 An error occurs during U...

Page 361: ...er m SSm Note If set the SSmn 1 to during a communication operation will wait status to stop the communication At this time holding status value of control register and shift register SCKmn and SOmn p...

Page 362: ...on instruction with STmL Reset signal generation clears the STm register to 0000H Figure 14 15 Format of Serial channel stop register m STm Note Holding status value of the control register and shift...

Page 363: ...n Channel n that stops operation can set the value of the CKOmn bit of the SOm register by software and output its value from the serial clock pin In this way any waveform such as that of a start cond...

Page 364: ...t condition and stop condition can be created by software The SOEm register can be set by a 16 bit memory manipulation instruction The lower 8 bits of the SOEm register can be set with a 1 bit or 8 bi...

Page 365: ...lue of the CKOmn bit can be changed only by a serial communication operation To use a pin for the serial interface as a port function pin other than a serial interface function pin set the correspondi...

Page 366: ...tion The lower 8 bits of the SOLm register can be set with an 8 bit memory manipulation instruction with SOLmL Reset signal generation clears the SOLm register to 0000H Figure 14 19 Format of Serial o...

Page 367: ...H0575EJ0120 Rev 1 20 Page 349 of 920 Dec 22 2016 Figure 14 20 Examples of Reverse Transmit Data a Non reverse Output SOLmn 0 b Reverse Output SOLmn 1 Transmit data ST P S SOLm 0 output SOUT0n Transmit...

Page 368: ...CK of the target channel 2 clock match detection is performed When the noise filter is OFF only synchronization is performed with the Operation clock of target channel fMCK The NFEN0 register can be s...

Page 369: ...to 1 When connecting an external device operating on a different potential 1 8 V 2 5 V or 3 V see 5 4 4 Handling different potential 1 8 V 2 5 V 3 V by using I O buffers Example When P02 SO10 TxD1 is...

Page 370: ...stop the operation of serial array unit 1 set bit 3 SAU1EN to 0 Figure 14 22 Peripheral Enable Register 0 PER0 Setting When Stopping the Operation by Units a Peripheral enable register 0 PER0 Set onl...

Page 371: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STm 0 0 0 0 0 0 0 0 0 0 0 0 STm3 0 1 STm2 0 1 STm1 0 1 STm0 0 1 1 Clears the SEmn bit to 0 and stops the communication operation Because the STmn bit is a trigge...

Page 372: ...transmit receive data MSB LSB first selectable Clock control Master slave selection Phase control of I O clock Setting of transfer period by prescaler and internal counter of each channel Maximum tran...

Page 373: ...y the master can be selected 3 wire serial I O CSIp performs the following seven types of communication operations Master transmission See 14 5 1 Master reception See 14 5 2 Master transmission recept...

Page 374: ...1 Channel 2 of SAU1 Pins used SCK10 SO10 SCK20 SO20 SCK21 SO21 SCK30 SO30 Interrupt INTCSI10 INTCSI20 INTCSI21 INTCSI30 Transfer end interrupt in single transfer mode or buffer empty interrupt in cont...

Page 375: ...er Interrupt source of channel n 0 Transfer end interrupt 1 Buffer empty interrupt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCRmn TXEmn 1 RXEmn 0 DAPmn 0 1 CKPmn 0 1 0 EOCmn 0 PTCmn1 0 PTCmn0 0 DIRmn 0 1...

Page 376: ...itial setting Setting a port register and a port mode register Enable data output and clock output of the target channel by Set the SSmn bit of the target channel to 1 SEmn bit 1 to enable operation S...

Page 377: ...the operation clock setting Re set the register to change the transfer baud rate setting setting the transfer clock by dividing the operation clock fMCK Re set the register to change serial mode regis...

Page 378: ...ming Chart of Master Transmission in Single Transmission Mode Type 1 DAPmn 0 CKPmn 0 Shift operation Shift operation Shift operation SSmn SEmn SDRmn STmn SCKp pin SOp pin Shift register mn INTCSIp TSF...

Page 379: ...r Number of communication data and Communication end flag are optionally set on the internal RAM by the software Enables interrupt Writing transmit data to SIOp SDRmn 7 0 Read transmit data from stora...

Page 380: ...gister mn SDRmn the transmit data is overwritten Caution The MDmn0 bit of serial mode register mn SMRmn can be rewritten even during operation However rewrite it before transfer of the last bit is sta...

Page 381: ...set on the internal RAM by the software Enables interrupt Writing transmit data to SIOp SDRmn 7 0 Read transmit data from storage area and write it to SIOp Update transmit data pointer Writing to SIO...

Page 382: ...Pins used SCK10 SI10 SCK20 SI20 SCK21 SI21 SCK30 SI30 Interrupt INTCSI10 INTCSI20 INTCSI21 INTCSI30 Transfer end interrupt in single transfer mode or buffer empty interrupt in continuous transfer mode...

Page 383: ...1 Prescaler output clock CKm1 set by the SPSm register Interrupt source of channel n 0 Transfer end interrupt 1 Buffer empty interrupt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCRmn TXEmn 0 RXEmn 1 DAPm...

Page 384: ...the target channel by setting a port register and a port mode register Set the SSmn bit of the target channel to 1 SEmn bit 1 to enable operation Initial setting is completed Set dummy data to the SI...

Page 385: ...operation clock setting Re set the register to change the transfer baud rate setting setting the transfer clock by dividing the operation clock fMCK Re set the register to change serial mode register...

Page 386: ...tion Mode Type 1 DAPmn 0 CKPmn 0 Receive data 3 Receive data 2 Receive data 1 Dummy data for reception Dummy data Dummy data Receive data 1 Receive data 2 Receive data 3 SSmn SEmn SDRmn STmn SCKp pin...

Page 387: ...rea of the receive data number of communication data Storage area Reception data pointer Number of communication data and Communication end flag are optionally set on the internal RAM by the software...

Page 388: ...ewritten before the transfer end interrupt of the last receive data Remark 1 to 8 in the figure correspond to 1 to 8 in Figure 14 39 Flowchart of Master Reception in Continuous Reception Mode 4 5 SSmn...

Page 389: ...nication data and Communication end flag are optionally set on the internal RAM by the software Enables interrupt Writing dummy data to SIOp SDRmn 7 0 Writing to SIOp makes SCKp signals out communicat...

Page 390: ...el 2 of SAU1 Pins used SCK10 SI10 SO10 SCK20 SI20 SO20 SCK21 SI21 SO21 SCK30 SI30 SO30 Interrupt INTCSI10 INTCSI20 INTCSI21 INTCSI30 Transfer end interrupt in single transfer mode or buffer empty inte...

Page 391: ...egister Interrupt source of channel n 0 Transfer end interrupt 1 Buffer empty interrupt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCRmn TXEmn 1 RXEmn 1 DAPmn 0 1 CKPmn 0 1 0 EOCmn 0 PTCmn1 0 PTCmn0 0 DIRm...

Page 392: ...e SSm register Completing initial setting Enable data output and clock output of the target channel by setting a port register and a port mode register Set the SSmn bit of the target channel to 1 SEmn...

Page 393: ...k by dividing the operation clock fMCK Re set the register to change serial mode register mn SMRmn setting Re set the register to change serial communication operation setting register mn SCRmn settin...

Page 394: ...n 0 Receive data 1 Receive data 2 Receive data 3 SSmn SEmn SDRmn STmn SCKp pin SIp pin Shift register mn INTCSIp TSFmn SOp pin Data transmission reception Data transmission reception Data transmission...

Page 395: ...ta for transmission reception data Storage area Transmission data pointer Reception data pointer Number of communication data and Communication end flag are optionally set on the internal RAM by the s...

Page 396: ...SMRmn can be rewritten even during operation However rewrite it before transfer of the last bit is started so that it has been rewritten before the transfer end interrupt of the last transmit data Re...

Page 397: ...ing dummy data to SIOp SDRmn 7 0 BFFmn 1 Buffer empty transfer end interrupt When transmission reception interrupt is generated it moves to interrupt processing routine No Except for initial interrupt...

Page 398: ...ation clock frequency of target channel 3 Wire Serial I O CSI10 CSI21 CSI30 Target channel Channel 2 of SAU0 Channel 1 of SAU1 Channel 2 of SAU1 Pins used SCK10 SO10 SCK21 SO21 SCK30 SO30 Interrupt IN...

Page 399: ...1 0 0 0 MDmn1 0 MDmn0 0 1 Operation clock fMCK of channel n 0 Prescaler output clock CKm0 set by the SPSm register 1 Prescaler output clock CKm1 set by the SPSm register Interrupt source of channel n...

Page 400: ...hannel Enable data output of the target channel by setting a port register and a port mode register Set the SSmn bit of the target channel to 1 SEmn bit 1 to enable operation Initial setting is comple...

Page 401: ...SOmn Set the SOEmn bit to 1 and enable output from the target channel Writing to the SSm register Changing setting of the SOEm register Selective Selective Selective Essential Essential Essential Esse...

Page 402: ...ming Chart of Slave Transmission in Single Transmission Mode Type 1 DAPmn 0 CKPmn 0 Shift operation Shift operation Shift operation SSmn SEmn SDRmn STmn SCKp pin SOp pin Shift register mn INTCSIp TSFm...

Page 403: ...ea Transmission data pointer Number of communication data and Communication end flag are optionally set on the internal RAM by the software Enables interrupt Writing transmit data to SIOp SDRmn 7 0 St...

Page 404: ...is 1 valid data is stored in serial data register mn SDRmn the transmit data is overwritten Caution The MDmn0 bit of serial mode register mn SMRmn can be rewritten even during operation However rewri...

Page 405: ...s interrupt Writing transmit data to SIOp SDRmn 7 0 Number of transmit data 1 Buffer empty transfer end interrupt When buffer empty transfer end interrupt is generated it moves to interrupt processing...

Page 406: ...S Remark fMCK Operation clock frequency of target channel 3 Wire Serial I O CSI10 CSI21 CSI30 Target channel Channel 2 of SAU0 Channel 1 of SAU1 Channel 2 of SAU1 Pins used SCK10 SI10 SCK21 SI21 SCK30...

Page 407: ...0 0 0 0 STSmn 0 0 SISmn0 0 1 0 0 0 MDmn1 0 MDmn0 0 Operation clock fMCK of channel n 0 Prescaler output clock CKm0 set by the SPSm register 1 Prescaler output clock CKm1 set by the SPSm register Inter...

Page 408: ...o 0000000B for baud rate setting Enable data input and clock input of the target channel by setting a port register and a port mode register Set the SSmn bit of the target channel to 1 SEmn bit 1 to e...

Page 409: ...ng of the SCRmn register Clearing error flag Completing resumption setting Re set the register to change the operation clock setting Re set the register to change serial mode register mn SMRmn setting...

Page 410: ...Slave Reception in Single Reception Mode Type 1 DAPmn 0 CKPmn 0 Receive data 3 Reception shift operation Reception shift operation Reception shift operation SSmn SEmn SDRmn STmn SCKp pin SIp pin Shif...

Page 411: ...0 Yes No Ready for reception Clear storage area setting and the number of receive data Storage area Reception data pointer Number of communication data and Communication end flag are optionally set on...

Page 412: ...rk fMCK Operation clock frequency of target channel 3 Wire Serial I O CSI10 CSI21 CSI30 Target channel Channel 2 of SAU0 Channel 1 of SAU1 Channel 2 of SAU1 Pins used SCK10 SI10 SO10 SCK21 SI21 SO21 S...

Page 413: ...mn CKSmn 0 1 CCSmn 1 0 0 0 0 0 STSmn 0 0 SISmn0 0 1 0 0 0 MDmn1 0 MDmn0 0 1 Operation clock fMCK of channel n 0 Prescaler output clock CKm0 set by the SPSm register 1 Prescaler output clock CKm1 set b...

Page 414: ...Set the SOEmn bit to 1 and enable data output of the target channel Enable data output of the target channel by setting a port register and a port mode register Set the SSmn bit of the target channel...

Page 415: ...er Re set the register to change the operation clock setting Re set the register to change serial mode register mn SMRmn setting Re set the register to change serial communication operation setting re...

Page 416: ...n 0 Reception shift operation Reception shift operation Reception shift operation SSmn SEmn SDRmn STmn SCKp pin SIp pin Shift register mn INTCSIp TSFmn SOp pin Data transmission reception Data transmi...

Page 417: ...number of data for transmission reception data Storage area Transmission reception data pointer Number of communication data and Communication end flag are optionally set on the internal RAM by the so...

Page 418: ...SMRmn can be rewritten even during operation However rewrite it before transfer of the last bit is started so that it has been rewritten before the transfer end interrupt of the last transmit data Re...

Page 419: ...ssion reception data pointer Number of communication data and Communication end flag are optionally set on the internal RAM by the software Enables interrupt BFFmn 1 Buffer empty transfer end interrup...

Page 420: ...le maximum transfer clock frequency is fMCK 6 Remark The value of SDRmn 15 9 is the value of bits 15 to 9 of serial data register mn SDRmn 0000000B to 1111111B and therefore is 0 to 127 The operation...

Page 421: ...0 0 1 fCLK 2 16 MHz 0 0 1 0 fCLK 22 8 MHz 0 0 1 1 fCLK 23 4 MHz 0 1 0 0 fCLK 24 2 MHz 0 1 0 1 fCLK 25 1 MHz 0 1 1 0 fCLK 26 500 kHz 0 1 1 1 fCLK 27 250 kHz 1 0 0 0 fCLK 28 125 kHz 1 0 0 1 fCLK 29 62 5...

Page 422: ...Manipulation Hardware Status Remark Reads serial data register mn SDRmn The BFFmn bit of the SSRmn register is set to 0 and channel n is enabled to receive data This is to prevent an overrun error if...

Page 423: ...elect the MSB LSB first Level setting of transmit receive data selecting whether to reverse the level Parity bit appending and parity check functions Stop bit appending stop bit check function Interru...

Page 424: ...fMCK Operation clock frequency of target channel fCLK System clock frequency UART UART1 UART3 Target channel Channel 2 of SAU0 Channel 2 of SAU1 Pins used TxD1 TxD3 Interrupt INTST1 INTST3 Transfer en...

Page 425: ...0 SMRmn CKSmn 0 1 CCSmn 0 0 0 0 0 0 0 0 0 1 0 0 0 MDmn1 1 MDmn0 0 1 Operation clock fMCK of channel n 0 Prescaler output clock CKm0 set by the SPSm register 1 Prescaler output clock CKm1 set by the SP...

Page 426: ...the target channel is set to 1 The value varies depending on the communication data during communication operation Remark 1 m Unit number m 0 1 n Channel number n 2 mn 02 12 q UART number q 1 3 Remark...

Page 427: ...to 1 and enable data output of the target channel Enable data output of the target channel by setting a port register and a port mode register Set the SSmn bit of the target channel to 1 and set the S...

Page 428: ...Re set the register to change the transfer baud rate setting setting the transfer clock by dividing the operation clock fMCK Re set the register to change serial mode register mn SMRmn setting Re set...

Page 429: ...Single Transmission Mode Remark m Unit number m 0 1 n Channel number n 2 q UART number q 1 3 mn 02 12 P Shift operation Shift operation Shift operation SP ST ST P SP ST P SP SSmn SEmn SDRmn TxDq pin...

Page 430: ...a to the SDRmn 7 0 bits TXDq register Read transmit data from storage area and write it to TxDq Update transmit data pointer Communication starts by writing to SDRmn 7 0 Transfer end interrupt When Tr...

Page 431: ...e MDmn0 bit of serial mode register mn SSRmn can be rewritten even during operation However rewrite it before transfer of the last bit is started so that it will be rewritten before the transfer end i...

Page 432: ...to the SDRmn 7 0 bits TXDq register Read transmit data from storage area and write it to TXDq Update transmit data pointer Communication starts by writing to SDRmn 7 0 Number of communication data 0...

Page 433: ...f target channel fCLK System clock frequency Remark 2 m Unit number m 0 1 n Channel number n 3 mn 03 13 UART UART1 UART3 Target channel Channel 3 of SAU0 Channel 3 of SAU1 Pins used RxD1 RxD3 Interrup...

Page 434: ...n 0 1 CCSmn 0 0 0 0 0 0 STSmn 1 0 SISmn0 0 1 1 0 0 0 MDmn1 1 MDmn0 0 Operation clock fMCK of channel n 0 Prescaler output clock CKm0 set by the SPSm register 1 Prescaler output clock CKm1 set by the S...

Page 435: ...nly the bits of the target channel is 1 Remark 1 m Unit number m 0 1 q UART number q 1 3 Remark 2 Setting disabled set to the initial value Bit that cannot be used in this mode set to the initial valu...

Page 436: ...eration mode etc Set a communication format Set a transfer baud rate setting the transfer clock by dividing the operation clock fMCK Set the SSmn bit of the target channel to 1 and set the Semn bit to...

Page 437: ...r Re set the register to change the operation clock setting Re set the register to change the transfer baud rate setting setting the transfer clock by dividing the operation clock fMCK Re set the regi...

Page 438: ...ion Remark m Unit number m 0 1 n Channel number n 3 mn 03 13 q UART number q 1 3 P Shift operation Shift operation Shift operation ST ST P ST P SP SP SP SSmn SEmn SDRmn STmn RxDq pin Shift register mn...

Page 439: ...y the software Enables interrupt Starting reception if start bit is detected Transfer end interrupt When receive complete transfer end interrupt is generated Indicating normal reception Reading receiv...

Page 440: ...mn SDRmn 15 9 0000000B 0000001B is prohibited Remark 1 When UART is used the value of SDRmn 15 9 is the value of bits 15 to 9 of the SDRmn register 0000010B to 1111111B and therefore is 2 to 127 Remar...

Page 441: ...0 fCLK 32 MHz 0 0 0 0 0 fCLK 32 MHz 0 0 0 1 fCLK 2 16 MHz 0 0 1 0 fCLK 22 8 MHz 0 0 1 1 fCLK 23 4 MHz 0 1 0 0 fCLK 24 2 MHz 0 1 0 1 fCLK 25 1 MHz 0 1 1 0 fCLK 26 500 kHz 0 1 1 1 fCLK 27 250 kHz 1 0 0...

Page 442: ...mn 02 12 q UART number q 1 3 Baud rate error Calculated baud rate value Target baud rate 100 100 UART Baud Rate Target Baud Rate fCLK 32 MHz Operation Clock fMCK SDRmn 15 9 Calculated Baud Rate Error...

Page 443: ...n 3 mn 03 13 q UART number q 1 3 Figure 14 87 Permissible Baud Rate Range for Reception 1 Data Frame Length 11 Bits As shown in Figure 14 87 the timing of latching receive data is determined by the di...

Page 444: ...ad from the SSRmn register to the SIRmn register without modification Software Manipulation Hardware Status Remark Reads serial data register mn SDRmn The BFFmn bit of the SSRmn register is set to 0 a...

Page 445: ...condition address transfer direction specification data and stop condition data to the slave device via the serial data bus The slave device automatically detects these received status and data by har...

Page 446: ...Match signal Match signal D Q Set Clear IICWL0 TRC0 DFC0 DFC0 SDAA0 P61 Start condition generator Stop condition generator Output control IICA low level width setting register 0 IICWL0 INTIICA0 IICCT...

Page 447: ...bus configuration example Figure 15 2 Serial Bus Configuration Example Using I2C Bus Remark n 0 1 Master CPU1 Slave CPU1 Address 0 SDAAn SCLAn Serial data bus Serial clock VDD SDAAn SCLAn SDAAn SCLAn...

Page 448: ...te data to the IICAn register during data transfer Caution 2 Write or read the IICAn register only during the wait period Accessing the IICAn register in a communication state other than during the wa...

Page 449: ...n an extension code is received 5 Serial clock counter This counter counts the serial clocks that are output or input during transmit receive operations and is used to verify that 8 bit data was trans...

Page 450: ...eleased IICBSYn bit 1 start condition requests are ignored and the STCFn bit is set to 1 12 Stop condition generator This circuit generates a stop condition when the SPTn bit is set to 1 13 Bus status...

Page 451: ...IICA is controlled by the following eight registers Peripheral enable register 0 PER0 IICA control register n0 IICCTLn0 IICA flag register n IICFn IICA status register n IICSn IICA control register n1...

Page 452: ...6 PM6 and port register 6 P6 IICA control register n0 IICCTLn0 IICA flag register n IICFn IICA status register n IICSn IICA control register n1 IICCTLn1 IICA low level width setting register n IICWLn...

Page 453: ...learing IICEn 0 Condition for setting IICEn 1 Cleared by instruction Reset Set by instruction LRELn Notes 2 3 Exit from communications 0 Normal operation 1 This exits from the current communications a...

Page 454: ...cks the clock is set to low level and wait is set for master device 1 Interrupt request is generated at the ninth clock s falling edge Master mode After output of nine clocks clock output is set to lo...

Page 455: ...isabled IICRSVn 1 Even if this bit is set 1 the STTn bit is cleared and the STTn clear flag STCFn is set 1 No start condition is generated In the wait state when master device Generates a restart cond...

Page 456: ...n cleared to 0 and slave has been notified of final reception For master transmission A stop condition cannot be generated normally during the acknowledge period Therefore set it during the wait perio...

Page 457: ...n a 1 bit memory manipulation instruction is executed for bits other than the IICSn register Therefore when using the ALDn bit read the data of this bit before the data of the other bits Remark 1 LREL...

Page 458: ...g COIn 1 When a start condition is detected When a stop condition is detected Cleared by LRELn 1 exit from communications When the IICEn bit changes from 1 to 0 operation stop Reset When the received...

Page 459: ...ng ACKDn 0 Condition for setting ACKDn 1 When a stop condition is detected At the rising edge of the next byte s first clock Cleared by LRELn 1 exit from communications When the IICEn bit changes from...

Page 460: ...0 Condition for setting STCFn 1 Cleared by STTn 1 When IICEn 0 operation stop Reset Generating start condition unsuccessful and the STTn bit cleared to 0 when communication reservation is disabled IIC...

Page 461: ...Enables operation of address match wakeup function in STOP mode To shift to STOP mode when WUPn 1 execute the STOP instruction at least three fMCK clocks after setting 1 the WUPn bit see Figure 15 28...

Page 462: ...was detected at low level 1 The SCLAn pin was detected at high level Condition for clearing CLDn 0 Condition for setting CLDn 1 When the SCLAn pin is at low level When IICEn 0 operation stop Reset Whe...

Page 463: ...of the time specified by IICWLn Figure 15 16 Format of IICA low level width setting register n IICWLn 15 3 7 IICA high level width setting register n IICWHn This register is used to set the high leve...

Page 464: ...register 6 PM6 and port register 6 P6 that controls the port functions for alternately used with SCLAn pin and SDAAn pin For details see 5 3 1 Port mode registers PMxx 5 3 2 Port registers Pxx and 5...

Page 465: ...slave devices Input is Schmitt input 2 SDAAn This pin is used for serial data input and output This pin is an N ch open drain output for both master and slave devices Input is Schmitt input Since outp...

Page 466: ...IICWHn 5 3 s tR tF fMCK When the fast mode plus IICWLn 0 50 s fMCK IICWHn 0 50 s tR tF fMCK Caution 1 The maximum operating frequency of the IICA operating clock fMCK is 20 MHz Max Only when fCLK exc...

Page 467: ...of the SDAAn and SCLAn signals separately because they differ depending on the pull up resistance and wire load Remark 2 IICWLn IICA low level width setting register n IICWHn IICA high level width se...

Page 468: ...tput by the master device However in the slave device the SCLAn pin low level period can be extended and a wait can be inserted 15 5 1 Start conditions A start condition is met when the SCLAn pin is a...

Page 469: ...vice operation Addresses are output when a total of 8 bits consisting of the slave address and the transfer direction described in 15 5 3 Transfer direction specification are written to the IICA shift...

Page 470: ...ICSn register is set by the data of the eighth bit that follows 7 bit address information Usually set the ACKEn bit to 1 for reception TRCn 0 If a slave can receive no more data during reception TRCn...

Page 471: ...ter device generates to the slave device when serial transfer has been completed When the device is used as a slave stop conditions can be detected Figure 15 24 Stop Condition A stop condition is gene...

Page 472: ...master and slave devices the next data transfer can begin Figure 15 25 Wait 1 2 1 When master device has a nine clock wait and slave device has an eight clock wait master transmits slave receives and...

Page 473: ...TLn0 register is set to 1 or when FFH is written to the IICA shift register n IICAn and the transmitting side cancels the wait state when data is written to the IICAn register The master device can al...

Page 474: ...gister to 1 To generate a restart condition after canceling a wait state set bit 1 STTn of the IICCTLn0 register to 1 To generate a stop condition after canceling a wait state set bit 0 SPTn of the II...

Page 475: ...e address register n SVAn and extension code is not received neither INTIICAn nor a wait occurs Remark The numbers in the table indicate the number of the serial clock s clock signals Interrupt reques...

Page 476: ...ion is detected only when SPIEn 1 15 5 9 Address match detection method In I2C bus mode the master device can select a particular slave device by transmitting the corresponding slave address Address m...

Page 477: ...ster n IICSn 3 Since the processing after the interrupt request occurs differs according to the data that follows the extension code such processing is performed by software If the extension code is r...

Page 478: ...n is set 1 via the timing by which the arbitration loss occurred and the SCLAn and SDAAn lines are both set to high impedance which releases the bus The arbitration loss is detected based on the timin...

Page 479: ...eighth or ninth clock following byte transfer Note 1 Read write data after address transmission During extension code transmission Read write data after extension code transmission During data transm...

Page 480: ...ility that an arbitration loss may change the master device which has generated a start condition to a slave device To use the wakeup function in the STOP mode set the WUPn bit to 1 Addresses can be r...

Page 481: ...next IIC communication Flow shown in Figure 15 30 When operating as a slave device for the next IIC communication When the INTIICAn interrupt is used to return from the mode Same as the flow in Figur...

Page 482: ...ecutes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA No Yes Releases STOP mode by an interrupt other than INTIICAn WUPn 1 START S...

Page 483: ...IICCTLn0 register was set to 1 and it was detected by generation of an interrupt request signal INTIICAn that the bus was released detection of the stop condition then the device automatically starts...

Page 484: ...ming shown in Figure 15 32 After bit 1 STDn of the IICA status register n IICSn is set to 1 a communication reservation can be made by setting bit 1 STTn of IICA control register n0 IICCTLn0 to 1 befo...

Page 485: ...n0 IICCTLn0 MSTSn Bit 7 of IICA status register n IICSn IICAn IICA shift register n IICWLn IICA low level width setting register n IICWHn IICA high level width setting register n tF SDAAn and SCLAn si...

Page 486: ...ated The following two statuses are included in the status where bus is not used When arbitration results in neither master nor slave operation When an extension code is received and slave operation i...

Page 487: ...low and the SCLAn pin is high the macro of I2C recognizes that the SDAAn pin has gone low detects a start condition If the value on the bus at this time can be recognized as an extension code ACK is r...

Page 488: ...bus released state This flowchart is broadly divided into the initial settings communication waiting and communication processing The processing when the RL78 G1H looses in arbitration and is specifi...

Page 489: ...TRCn 1 ACKDn 1 ACKDn 1 Sets a transfer clock Sets a local address Sets a start condition Starts communication specifies an address and transfer direction Waits for detection of acknowledge Waits for...

Page 490: ...s a transfer clock Sets a local address Sets a start condition Communication start request No communication start request Waiting to be specified as a slave by other master Waiting for a communication...

Page 491: ...COIn 1 Prepares for starting communication generates a start condition Waits for bus release communication being reserved Wait state after stop condition was detected and start condition was generated...

Page 492: ...rred and determine the processing to be performed next Remark 4 n 0 1 Communication processing C Writing IICAn WTIMn 1 WRELn 1 Reading IICAn ACKEn 1 WTIMn 0 Writing IICAn Yes TRCn 1 Restart MSTSn 1 St...

Page 493: ...ation mode flag This flag indicates the following two communication statuses Clear mode Status in which data communication is not performed Communication mode Status in which data communication is per...

Page 494: ...ssion and reception formats Remark2 n 0 1 Communication direction flag 1 Communication direction flag 1 Ready flag 1 ACKDn 1 Communication mode flag 1 Writing IICAn Clearing communication mode flag WR...

Page 495: ...ress does not match If the address matches the communication mode is set wait is cancelled and processing returns from the interrupt the ready flag is cleared 3 For data transmit receive only the read...

Page 496: ...nce The timing of transmitting or receiving data and generation of interrupt request signal INTIICAn and the value of the IICA status register n IICSn when the INTIICAn signal is generated are shown b...

Page 497: ...3 IICSn 1000 000B Sets the WTIMn bit to 1 Note 4 IICSn 1000 00B Sets the SPTn bit to 1 5 IICSn 00000001B Note To generate a stop condition set the WTIMn bit to 1 and change the timing for generating t...

Page 498: ...e SPTn bit to 1 7 IICSn 00000001B Note 1 To generate a start condition set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt request signal Note 2 Clear the WTIMn bit to 0...

Page 499: ...000B Sets the WTIMn bit to 1 Note 4 IICSn 1010 00B Sets the SPTn bit to 1 5 IICSn 00000001B Note To generate a stop condition set the WTIMn bit to 1 and change the timing for generating the INTIICAn...

Page 500: ...IMn 1 Remark n 0 1 ST AD6 to AD0 D7 to D0 R W ACK ACK SP D7 to D0 ACK 4 1 2 3 1 IICSn 0001 110B 2 IICSn 0001 000B 3 IICSn 0001 000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn...

Page 501: ...D0 D7 to D0 R W ACK ACK SP ST AD6 to AD0 D7 to D0 R W ACK ACK 5 4 3 2 1 1 IICSn 0001 110B 2 IICSn 0001 000B 3 IICSn 0001 110B 4 IICSn 0001 000B 5 IICSn 00000001B Remark Always generated Generated only...

Page 502: ...AD6 to AD0 D7 to D0 R W ACK ACK SP ST AD6 to AD0 D7 to D0 R W ACK ACK 5 1 2 3 4 1 IICSn 0001 110B 2 IICSn 0001 000B 3 IICSn 0010 010B 4 IICSn 0010 000B 5 IICSn 00000001B Remark Always generated Gener...

Page 503: ...not extension code Remark n 0 1 ST AD6 to AD0 D7 to D0 R W ACK ACK SP ST AD6 to AD0 D7 to D0 R W ACK ACK 4 1 2 3 1 IICSn 0001 110B 2 IICSn 0001 000B 3 IICSn 00000110B 4 IICSn 00000001B Remark Always...

Page 504: ...a Stop i When WTIMn 0 ii When WTIMn 1 Remark n 0 1 ST AD6 to AD0 D7 to D0 R W ACK ACK SP D7 to D0 ACK 4 3 2 1 1 IICSn 0010 010B 2 IICSn 0010 000B 3 IICSn 0010 000B 4 IICSn 00000001B Remark Always gene...

Page 505: ...ACK ACK SP ST AD6 to AD0 D7 to D0 R W ACK ACK 5 1 2 3 4 1 IICSn 0010 010B 2 IICSn 0010 000B 3 IICSn 0001 110B 4 IICSn 0001 000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Do...

Page 506: ...ACK ACK SP ST AD6 to AD0 D7 to D0 R W ACK ACK 5 1 2 3 4 1 IICSn 0010 010B 2 IICSn 0010 000B 3 IICSn 0010 010B 4 IICSn 0010 000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Do...

Page 507: ...on code Remark n 0 1 ST AD6 to AD0 D7 to D0 R W ACK ACK SP ST AD6 to AD0 D7 to D0 R W ACK ACK 4 3 2 1 1 IICSn 0010 010B 2 IICSn 0010 000B 3 IICSn 00000 10B 4 IICSn 00000001B Remark Always generated Ge...

Page 508: ...STSn bit each time interrupt request signal INTIICAn has occurred to check the arbitration result a When arbitration loss occurs during transmission of slave address data i When WTIMn 0 Remark n 0 1 S...

Page 509: ...mark n 0 1 ST AD6 to AD0 D7 to D0 R W ACK ACK SP D7 to D0 ACK 4 1 2 3 1 IICSn 0101 110B 2 IICSn 0001 100B 3 IICSn 0001 00B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t c...

Page 510: ...NTIICAn has occurred to check the arbitration result a When arbitration loss occurs during transmission of slave address data when WTIMn 1 Remark n 0 1 ST AD6 to AD0 D7 to D0 R W ACK ACK SP D7 to D0 A...

Page 511: ...uring transmission of data i When WTIMn 0 Remark n 0 1 ST AD6 to AD0 D7 to D0 R W ACK ACK SP D7 to D0 ACK 2 1 1 IICSn 0110 010B Sets LRELn 1 by software 2 IICSn 00000001B Remark Always generated Gener...

Page 512: ...ple unmatches with SVAn Remark n 0 1 ST AD6 to AD0 D7 to D0 R W ACK SP D7 to D0 ACK ACK 3 1 2 1 IICSn 10001110B 2 IICSn 01000100B 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1...

Page 513: ...k n 0 1 ST AD6 to AD0 D7 to Dm R W ACK SP D7 to D0 ACK ST AD6 to AD0 R W ACK 3 2 1 1 IICSn 1000 110B 2 IICSn 01100010B Sets LRELn 1 by software 3 IICSn 00000001B Remark Always generated Generated only...

Page 514: ...to D0 ACK STTn 1 D7 to D0 ACK 5 3 4 2 1 1 IICSn 1000 110B 2 IICSn 1000 000B Sets the WTIMn bit to 1 3 IICSn 1000 100B Clears the WTIMn bit to 0 4 IICSn 01000000B 5 IICSn 00000001B Remark Always gener...

Page 515: ...rk n 0 1 ST AD6 to AD0 D7 to D0 R W ACK ACK SP STTn 1 4 1 2 3 1 IICSn 1000 110B 2 IICSn 1000 000B Sets the WTIMn bit to 1 3 IICSn 1000 00B Sets the STTn bit to 1 4 IICSn 01000001B Remark Always genera...

Page 516: ...o D0 ACK SPTn 1 D7 to D0 ACK 5 1 2 3 4 1 IICSn 1000 110B 2 IICSn 1000 000B Sets the WTIMn bit to 1 3 IICSn 1000 100B Clears the WTIMn bit to 0 4 IICSn 01000100B 5 IICSn 00000001B Remark Always generat...

Page 517: ...ts the TRCn bit bit 3 of the IICA status register n IICSn which specifies the data transfer direction and then starts serial communication with the slave device Figures 15 40 to 15 46 show timing char...

Page 518: ...fast mode Note 3 For releasing wait state during reception of a slave device write FFH to IICAn or set the WRELn bit Remark n 0 1 ACKDn ACK detection IICAn WTIMn 8 or 9 clock wait ACKEn ACK control M...

Page 519: ...TIICAn end of address transmission at the falling edge of the 9th clock The slave device whose address matched the transmitted slave address sets a wait status SCLAn 0 and issues an interrupt INTIICAn...

Page 520: ...he WRELn bit Remark n 0 1 ACKDn ACK detection IICAn WTIMn 8 or 9 clock wait ACKEn ACK control MSTSn communication status STTn ST trigger SPTn SP trigger WRELn wait cancellation INTIICAn interrupt Bus...

Page 521: ...ected by the master device ACKDn 1 at the rising edge of the 9th clock 8 The master device and slave device set a wait status SCLAn 0 at the falling edge of the 9th clock and both the master device an...

Page 522: ...mode Note 3 For releasing wait state during reception of a slave device write FFH to IICAn or set the WRELn bit Remark n 0 1 ACKDn ACK detection IICAn WTIMn 8 or 9 clock wait ACKEn ACK control MSTSn...

Page 523: ...the master device The ACK is detected by the master device ACKDn 1 at the rising edge of the 9th clock 12 The master device and slave device set a wait status SCLAn 0 at the falling edge of the 9th c...

Page 524: ...tion of a slave device write FFH to IICAn or set the WRELn bit Remark n 0 1 ACKDn ACK detection IICAn WTIMn 8 or 9 clock wait ACKEn ACK control MSTSn communication status STTn ST trigger SPTn SP trigg...

Page 525: ...An 0 at the falling edge of the 9th clock and both the master device and slave device issue an interrupt INTIICAn end of transfer i The slave device reads the received data and releases the wait statu...

Page 526: ...to IICAn not setting the WRELn bit in order to cancel a wait state during transmission by a slave device Remark n 0 1 ACKDn ACK detection IICAn WTIMn 8 or 9 clock wait ACKEn ACK control MSTSn communic...

Page 527: ...dge of the 9th clock The slave device whose address matched the transmitted slave address sets a wait status SCLAn 0 and issues an interrupt INTIICAn address match Note 5 The timing at which the maste...

Page 528: ...ark n 0 1 ACKDn ACK detection IICAn WTIMn 8 or 9 clock wait ACKEn ACK control MSTSn communication status STTn ST trigger SPTn SP trigger WRELn wait cancellation INTIICAn interrupt Bus line TRCn transm...

Page 529: ...nsfer Because of ACKEn 1 in the master device the master device then sends an ACK by hardware to the slave device 9 The master device reads the received data and releases the wait status WRELn 1 10 Th...

Page 530: ...mission by a slave device Note 4 If a wait state during transmission by a slave device is canceled by setting the WRELn bit the TRCn bit will be cleared Remark n 0 1 ACKDn ACK detection IICAn WTIMn 8...

Page 531: ...status to the 9th clock WTIMn 1 15 If the master device releases the wait status WRELn 1 the slave device detects the NACK ACKDn 0 at the rising edge of the 9th clock 16 The master device and slave de...

Page 532: ...cluding general purpose registers mirror area Note data flash memory area Note extended special function register 2nd SFR Destinations Special function register SFR RAM area excluding general purpose...

Page 533: ...it in the DTCCRj register is 1 interrupt generation enabled the activation source interrupt request is generated for the CPU and interrupt handling is performed on completion of the transfer Transfer...

Page 534: ...22 2016 16 2 Configuration of DTC Figure 16 1 shows the DTC Block Diagram Figure 16 1 DTC Block Diagram Internal bus DTCENi DTCBAR Data transfer control RAM Control data vector table Interrupt source...

Page 535: ...ol data is stored Remark j 0 to 23 Table 16 2 Registers Controlling DTC Register Name Symbol Peripheral enable register 1 PER1 DTC activation enable register 0 DTCEN0 DTC activation enable register 1...

Page 536: ...area Caution 2 Make sure the stack area the DTC control data area and the DTC vector table area do not overlap Caution 3 The internal RAM area in the following products cannot be used as the DTC cont...

Page 537: ...access DTCCRj DTBLSj DTCCTj DTRLDj DTSARj or DTDARj using a DTC transfer Figure 16 3 Control Data Allocation Table 16 4 Start Address of Control Data j Address j Address 11 Fxx98H 23 FxxF8H 10 Fxx90H...

Page 538: ...wer 8 bits corresponding to the activation source Change the start address of the DTC control data area to be set in the vector table when the corresponding bit among bits DTCENi0 to DTCENi7 i 0 to 4...

Page 539: ...nd CSI30 transfer end or buffer empty 18 Address set in DTCBAR register 12H End of channel 0 of timer array unit 0 count or capture 19 Address set in DTCBAR register 13H End of channel 1 of timer arra...

Page 540: ...o as to decrease the power consumption and noise When using the DTC be sure to set bit 3 DTCEN to 1 The PER1 register can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal genera...

Page 541: ...INT bit is invalid when the MODE bit is 0 normal mode CHNE Enabling disabling chain transfers 0 Chain transfers disabled 1 Chain transfers enabled Set the CHNE bit in the DTCCR23 register to 0 chain t...

Page 542: ...of DTC transfer count register j DTCCTj Caution Do not access the DTCCTj register using a DTC transfer Address Refer to 16 3 2 Control Data Allocation After reset Undefined R W Symbol 7 6 5 4 3 2 1 0...

Page 543: ...ansfer 16 3 10 DTC destination address register j DTDARj j 0 to 23 This register is used to specify the transfer destination address for data transfer When the SZ bit in the DTCCRj register is set to...

Page 544: ...EN0 F02E9H DTCEN1 F02EAH DTCEN2 After reset 00H R W F02EBH DTCEN3 F02ECH DTCEN4 Symbol 7 6 5 4 3 2 1 0 DTCENi DTCENi7 DTCENi6 DTCENi5 DTCENi4 DTCENi3 DTCENi2 DTCENi1 DTCENi0 DTCENi7 DTC activation ena...

Page 545: ...sabled by a condition for generating a transfer end interrupt DTCENi1 DTC activation enable i1 0 Activation disabled 1 Activation enabled The DTCENi1 bit is set to 0 activation disabled by a condition...

Page 546: ...sfer end or buffer empty CSI21 transfer end or buffer empty DTCEN2 CSI20 transfer end or buffer empty UART3 reception transfer end UART3 transmission transfer end CSI30 transfer end or buffer empty En...

Page 547: ...ster DTCBAR 16 4 DTC Operation When the DTC is activated control data is read from the DTC control data area to perform data transfers and control data after data transfer is written back to the DTC c...

Page 548: ...e 0 is not written to the bit among bits DTCENi0 to DTCENi7 for data transfers activated by the setting to enable chain transfers the CHNE bit is 1 Also no interrupt request is generated Transfer data...

Page 549: ...sing the RAM parity error detection function Remark j 0 to 23 Figure 16 15 Data Transfers in Normal Mode Table 16 7 Register Functions in Normal Mode Register Name Symbol Function DTC block size regis...

Page 550: ...ion and sets the corresponding bit among bits DTCENi0 to DTCENi7 to 0 activation disabled When the RPTINT bit in the DTCCRj register is 0 interrupt generation disabled no interrupt request is generate...

Page 551: ...Destination Address after Transfer DAMOD SAMOD RPTSEL MODE 0 X 1 1 Repeat area Fixed SRC N DST 1 X 1 1 Repeat area Incremented SRC N DST N X 0 0 1 Fixed Repeat area SRC DST N X 1 0 1 Incremented Repea...

Page 552: ...g multiple control data the number of transfers set for the first control data is enabled and the number of transfers set for the second and subsequent control data to be processed will be invalid Fig...

Page 553: ...llocate RAM addresses which are used as a DTC transfer destination transfer source to the area FFE20H to FFEDFH when performing self programming and rewriting the data flash memory 16 5 2 Allocation o...

Page 554: ...s for IFxx MKxx PRxx and PSW and an 8 bit manipulation instruction that has the ES register as operand Instruction for accessing the data flash memory Caution 1 When a DTC transfer request is acknowle...

Page 555: ...ack Operation DTCCR Register Setting Address Setting Control Register to be Written Back Number of Clock Cycles DAMOD SAMOD RPTSEL MODE Source Destination DTCCTj Register DTRLDj Register DTSARj Regist...

Page 556: ...time for each condition execution clock cycles for the instruction to be held pending under the condition When accessing the TRJ0 register that a wait occurs Maximum response time Maximum response ti...

Page 557: ...a flash memory are stopped during the SNOOZE mode the flash memory cannot be set as the transfer source Note 3 When an A D conversion end interrupt is set as a DTC activation source from the A D conve...

Page 558: ...each peripheral function By linking events it becomes possible to coordinate operation between peripheral functions directly without going through the CPU 17 2 Configuration of ELC Figure 17 1 shows...

Page 559: ...nit 0 channel 0 as the link destination peripheral function set the operating clock for channel 0 to fCLK using timer clock select register 0 TPS0 set the noise filter of the TI00 pin to OFF TNFEN00 0...

Page 560: ...al interrupt edge detection 3 INTP3 ELSELR04 External interrupt edge detection 4 INTP4 ELSELR07 RTC fixed cycle signal Alarm match detection INTRTC ELSELR13 Timer RJ0 underflow INTTRJ0 ELSELR16 TAU ch...

Page 561: ...ween Interrupt Handling and ELC Note Not available depending on the peripheral function Table 17 2 lists the response of peripheral functions that receive events Table 17 2 Response of Peripheral Func...

Page 562: ...ec 22 2016 CHAPTER 18 RF TRANSCEIVER Precautions for use of RF transceiver The international standard and the domestic laws and regulations restrict use of the wireless receiver and transmitter Be sur...

Page 563: ...res Low power consumption RF receiving current 6 9 mA TYP 3 0 V 100 kbps 2FSK at STOP mode of MCU RF transmission current 21 mA TYP 3 0 V 100 kbps 2FSK 10 dBm at STOP mode of MCU Transceiver RF freque...

Page 564: ...o REFCLKIN pin For this connection connect XIN pin to GND on the board via the 100 pF decoupling capacitor 3 INTOUT This is an interrupt output pin of RF transceiver When the interrupt source is gener...

Page 565: ...GPIO3 I O Transceiver I O port 3 35 GPIO4 ANTSW I O Transceiver I O port 4 and ANTSW pin 36 VREGO2 Stabilization capacitor connection pin for VCO 1 1 V 37 VREGO3 Power supply stabilization capacitor c...

Page 566: ...with the SPI function for interfacing with MCU For details see 18 5 3 Pin control block Controls I O etc of pins SIN VCCRF DDCOUT VCCDDC SOUT SCLK SEN VSSDDC Analog block CONTROL PLL Modulator VCO MA...

Page 567: ...block This block controls the input amplitudes under the constant state that are transmitted to the AD converter which is connected to the subsequent stage by changing the gain depending on the input...

Page 568: ...e oscillation stop until the stabilization The oscillation stabilization time requires the stabilization wait time 500 s varies depending on the oscillation circuit REFCLKIN_RF external clock This clo...

Page 569: ...Demodulation block RF receive control Frame control storage Sequence number storage Address match detection circuit Control register group Interrupt control Timer AGC control Receive RAM ACK reply co...

Page 570: ...h ranged from the minimum 3 bytes to the maximum 2047 bytes The data written in the transmission RAM is output sequentially Note that the CR data which is generated in the CRC calculation circuit is a...

Page 571: ...2FSK 2GFSK 40 0 5 4 2FSK 2GFSK 50 1 4 2FSK 2GFSK 100 0 5 4 2FSK 2GFSK 100 1 4 2FSK 2GFSK 150 0 5 5 2FSK 2GFSK 200 0 5 6 2FSK 2GFSK 200 1 6 2FSK 2GFSK 300 0 5 7 4FSK 4GFSK 100 0 33 5 4FSK 4GFSK 200 0...

Page 572: ...ase Other Than the Mode Switch Frame MS Mode Switch Mode switch enable bit value Mode switch frame transmission register bit 0 Automatically transmits the following values when this bit value is 0 R1...

Page 573: ...n in the Case of the Mode Switch Frame MS Mode Switch Mode switch enable bit value Mode switch frame transmission register bit 0 Automatically transmits the following values when this bit value is 1 M...

Page 574: ...n Interrupt request occurs when transmit RAM data transmission of bank 0 completes 6 Bank 1 transmit completion Interrupt request occurs when transmit RAM data transmission of bank 1 completes 7 CCA c...

Page 575: ...address register 0 BBSHORTAD0 0017H 0016H FFFFH 20 Extended address register 0 BBEXTENDAD03 001FH 001EH 0000H BBEXTENDAD02 001DH 001CH 0000H BBEXTENDAD01 001BH 001AH 0000H BBEXTENDAD00 0019H 0018H 00...

Page 576: ...0000H 62 PHY header receive register BBPHRRX 00BEH 00H 63 Preamble setting register BBPABL 00C1H 00C0H 00AAH 64 SFD setting register BBSFD 00C5H 00C2H 00007209H 65 SHR control register BBSHRCON 00C6H...

Page 577: ...nsists of 8 bits and can be accessed serial interface communication in 8 bit unit Reset signal generation sets this register to 01H Figure 18 7 RF Start Register BBRFCON Format Caution Be sure to clea...

Page 578: ...ared to 0 However the values of the respective registers can be retained Reset by RFRESETB pin after setting RFSTOP bit to 1 for stopping transmission The BBTXRXRST register is set by the serial inter...

Page 579: ...automatically transit to the receive mode after the completion of receive by using the automatic receive switch mode 1 enable bit However note that the ACK reply takes precedence if all of the ACK rep...

Page 580: ...EACON BEACON mode bit 0 Non beacon mode 1 BEACON mode BATLIFEEXT Battery life extension mode bit 0 Battery life extension mode disabled 1 Battery life extension mode enabled AUTORCV1 Automatic receive...

Page 581: ...pon automatic ACK reply when the ACK reply frame version setting enable bit 1 The ACK replay frame version setting bit 1 can be used to set the value of bit 13 for the frame version value upon automat...

Page 582: ...bit 0 Upon completion of the receive 1 Upon reception of the PHR SQCNUMSU PEN Sequence number suppress bit 0 Sequence number suppress enabled 1 Sequence number suppress disabled ACKFV1 ACK reply fram...

Page 583: ...al revel defers causing LSI board layout and usage of RFSW or SAW filter Therefore setting values are required modification to match the input level and value of RSSI CCA result register BBRSSICCARSLT...

Page 584: ...0 84 8C 0A 1B 0F 03 34 005 20 88 90 04 1A 0F 03 34 006 40 8C 94 04 1A 0F 03 34 6 901MHz US 007 10 84 8C 0A 1B 0F 03 34 008 20 88 90 04 1A 0F 03 34 009 40 8C 94 04 1A 0F 03 34 7 915MHz US 010 50 8D 95...

Page 585: ...0 85 8D 0B 1B 0F 03 34 005 20 89 91 05 1A 0F 03 34 006 40 8D 95 05 1A 0F 03 34 6 901MHz US 007 10 85 8D 0B 1B 0F 03 34 008 20 89 91 05 1A 0F 03 34 009 40 8D 95 05 1A 0F 03 34 7 915MHz US 010 50 8E 96...

Page 586: ...0 86 8E 0C 1B 0F 03 34 005 20 8A 92 06 1A 0F 03 34 006 40 8E 96 06 1A 0F 03 34 6 901MHz US 007 10 86 8E 0C 1B 0F 03 34 008 20 8A 92 06 1A 0F 03 34 009 40 8E 96 06 1A 0F 03 34 7 915MHz US 010 50 8F 97...

Page 587: ...0 87 8F 0D 1B 0F 03 34 005 20 8B 93 07 1A 0F 03 34 006 40 8F 97 07 1A 0F 03 34 6 901MHz US 007 10 87 8F 0D 1B 0F 03 34 008 20 8B 93 07 1A 0F 03 34 009 40 8F 97 07 1A 0F 03 34 7 915MHz US 010 50 90 98...

Page 588: ...s and can be accessed serial interface communication in 8 bit unit Reset signal generation sets this register to 01H Figure 18 12 Enhanced ACK Mode Register BBEACKMODE Format Caution Be sure to clear...

Page 589: ...ed The receive RAM bank 0 status bit and the receive RAM bank 1 status bit can be used as flags upon data capture for the respective receive RAM banks 0 and 1 1 is automatically set upon completion of...

Page 590: ...A CRC CCA RCVRAMST Receive RAM bank pointer bit 0 Receive RAM bank 0 1 Receive RAM bank 1 RCVPEND Receive pending bit 0 No pending 1 Pending exists RCVBANK1 Receive RAM bank 1 status bit 0 Receive ena...

Page 591: ...ve data save bank select bit is read upon reading because this bit left the result of the automatic ACK reply for every received save bank The enhanced ACK enable bit can be used to support the enhanc...

Page 592: ...vel filter interrupt occurs An overwrite enable processing might be required depending on the destroyed timing Then changing to enable reception of receive bank 0 1 status bits for corresponding bank...

Page 593: ...ose mode ADFEXTEN Address filter address extension bit 0 PANID Address expansion disabled 1 PANID Address expansion enabled RCVOVERW REN Receive RAM overwrite enable bit 0 Overwrite disabled 1 Overwri...

Page 594: ...es 1 after reset or initialization The BBTXRXST1 register is read by the serial interface in 8 bit units Reset signal generation clears this register to 02H Figure 18 16 Transmit Receive Status Regist...

Page 595: ...r of CCA Stop the reception by using the RF communication stop bit when you want to stop the operation in the middle Do not stop transmission during the operation The automatic ACK receive mode bit ca...

Page 596: ...wait time for the CCA operation in the CSMA CA operation The back off period count stops during a frame reception The unicast frame bit sets the unicast frame value Setting 1 to the unicast frame enab...

Page 597: ...as 2 s complement The setting unit is dBm ex 19EH is 98dBm The BBCCAVTH register is set by the serial interface in 8 bit units Reset signal generation sets this register to 0100H Figure 18 19 CCA Leve...

Page 598: ...on storage bank upon start of the reception The BBTXRXST2 register consists of 8 bits and can be accessed serial interface communication in 8 bit unit Reset signal generation sets this register to 03H...

Page 599: ...on completion of the CSMA CS sequence The INT output polarity switch bit can be used to select the interrupt polarity of the interrupt output from the INTOUT pin Automatic receive with timeout after t...

Page 600: ...UTIN TSEL Receive timeout interrupt switch bit 0 Byte receive interrupt 1 Receive timeout interrupt TIMEOUTR CV Automatic receive with timeout after transmit enable bit 0 Automatic normal reception mo...

Page 601: ...t is used to set the CW value Initial value is 2H The BBCSMACON1 register consists of 8 bits and can be accessed serial interface communication in 8 bit unit Reset signal generation sets this register...

Page 602: ...icast frame enable bit can be used to set the operation by the unicast frame bit The BBCSMACON2 register consists of 8 bits and can be accessed serial interface communication in 8 bit unit Reset signa...

Page 603: ...er 0 BBPANID0 Format 19 Short address register 0 BBSHORTAD0 This register is used to set the short address of the first address filter It consists of 16 bits and is used to detect the match with a rec...

Page 604: ...ters to 0000H Figure 18 26 Extended Address Register 0 BBEXTENDAD00 to BBEXTENDAD03 Format Address 001FH 001EH After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 BBEXTEN DAD03 7 6 5 4 3 2 1 0 BBEXTEND...

Page 605: ...IMEREAD0 and BBTIMEREAD1 registers consist of 16 bits and can be accessed serial interface communication in 8 bit unit Reset signal generation clears these registers to 0000H Figure 18 27 Timer Read R...

Page 606: ...t Reset signal generation clears these registers to 0000H Figure 18 29 Timer Compare Register 0 BBTCOMP0REG0 to BBTCOMP2REG0 Format Figure 18 30 Timer Compare Register 1 BBTCOMP0REG1 to BBTCOMP2REG1 F...

Page 607: ...stamp value corresponding to the save bank which is specified by the receive data save bank select bit is read out when reading In addition the timer count upon completion of the transmission is autom...

Page 608: ...state they are IDLE The stamp timing switch bit can be used to select the stamp timing of the timer value The value is updated at the timing of receive start regardless of the address filter function...

Page 609: ...e switch bit 0 Prescaler output 1 s 1 Data rate STAMPRDS EL1 STAMPRDS EL0 Stamp value read switch bit 0 0 Receive start stamp value 0 1 Receive completion stamp value 1 0 Transmit completion stamp val...

Page 610: ...et the random value to the back off period register 2 and then set 1 to the back off period auto random enable bit of the back off period register The BBBOFFPROD register consists of 8 bits and can be...

Page 611: ...aseband interrupt source registers 0 to 2 BBINTREQ0 to BBINTREQ2 continuously leave SEN internal pin low level Figure 18 35 Baseband Interrupt Source Register 0 BBINTREQ0 Format Caution Bit 6 is X und...

Page 612: ...that there is an interrupt request When reading this register only the bit from which 1 is read is cleared to 0 Note that perform the dummy read when you clear the bit because writing is disabled The...

Page 613: ...ts MODESWINTREQ Mode switch receive completion interrupt source bit 0 No request 1 Request exists ROVRINTREQ Receive overrun interrupt source bit 0 No request 1 Request exists ADRSINTREQ Address filte...

Page 614: ...and can be accessed serial interface communication in 8 bit unit Note Reset signal generation clears this register to 00H Note When reading this register read 3 bytes of the baseband interrupt source...

Page 615: ...band Interrupt Enable Register 0 BBINTEN0 Format Caution Be sure to clear bit 6 to 0 It is read as x undefined Address 0039H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 BBINTEN0 CCAINTEN X TRN1INTEN TR...

Page 616: ...s this register to 00H Figure 18 39 Baseband Interrupt Enable Register 1 BBINTEN1 Format Address 003AH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 BBINTEN1 LVLFILINTEN MODESWINTEN ROVRINTEN ADRSINTEN R...

Page 617: ...INTEN2 register is set by the serial interface in 8 bit units Reset signal generation clears this register to 00H Figure 18 40 Baseband Interrupt Enable Register 2 BBINTEN2 Format Caution Be sure to c...

Page 618: ...the BEMAX bit setting value Set value other than 0H to these bits to perform CCA The BBCSMACON3 register consists of 8 bits and can be accessed serial interface communication in 8 bit unit Reset signa...

Page 619: ...erial interface communication in 8 bit unit Reset signal generation sets ACKCOMP0 to 0014H and sets ACKCOMP1 to 000EH Figure 18 42 ACK Counter Compare Register 0 ACKCOMP0 Format Figure 18 43 ACK Count...

Page 620: ...300 s from the back off cycle Initial value 0014H 20 symbols Set value 1H 1 symbol ACK counter compare 1 register Set the time subtracted 144 s from the back off cycle Initial value 000EH 15 symbols...

Page 621: ...ate and value of RSSI CCA result register BBRSSICCARSLT For details see 18 4 4 5 RSSI CCA result register BBRSSICCARSLT The BBLVLVTH register is set by the serial interface in 8 bit units Reset signal...

Page 622: ...ompletion of packet receive to the TRG_ON time Initial value 0002H 2 symbols Set value 1H 1 symbol Counter stops and H is set to the TRG_ON signal when the 10 bit timer for the ACK reply mode starts f...

Page 623: ...consists of 16 bits and can be accessed serial interface communication in 8 bit unit Reset signal generation sets this register to 000AH Figure 18 49 Automatic Receive Switch Compare Register AUTORCV...

Page 624: ...1H 113 symbols Set value 1H 1 symbol The BOFFPERIOD register consists of 16 bits and can be accessed serial interface communication in 8 bit unit Reset signal generation sets this register to 0071H Fi...

Page 625: ...ence is used Initial value is 0080H 128 s Set value 1H 1 s The CSMAENDCOUNT register consists of 16 bits and can be accessed serial interface communication in 8 bit unit Reset signal generation sets t...

Page 626: ...m number of symbols which is greater than 144 s Initial value 000EH 15 symbols Set value 1H 1 symbol The CSMASTACOUNT register consists of 16 bits and can be accessed serial interface communication in...

Page 627: ...it shows CCA state Receiving frame status bit shows frame receive state Figure 18 54 Communication status register 1 COMSTATE1 Format Caution Bits 0 4 to 7 are read as x undefined Address 0066H After...

Page 628: ...is used to confirm each state in communication ACK reply status bit shows ACK reply state Figure 18 55 Communication status register 2 COMSTATE2 Format Caution Bits 1 to 7 are read as x undefined Add...

Page 629: ...ous receive mode the completion of the data reception cannot enter into the IDLE state The receive state is left as it is Setting 1 to both special transmission mode and transmit trigger bit can trans...

Page 630: ...e switch frame transmit register Be sure to set bits 0 and 4 of the mode switch frame transmit register to 0 Transmits data regardless of the MODESW bit value Transmits data regardless of the transmit...

Page 631: ...bit and bit 4 corresponds to DW bit of the first byte of PHR can be received only 0s Receives data regardless of the MODESW bit value Ignores the received frame length Receive data part Stores the rec...

Page 632: ...gister 2 and then set 1 to the back off period auto random enable bit of the back off period register The BBBOFFPROD2 register consists of 8 bits and can be accessed serial interface communication in...

Page 633: ...ng the CCA can be read by using the number of CCA time read bit The COMSTATE3 register consists of 8 bits and can be accessed serial interface communication in 8 bit unit Reset signal generation clear...

Page 634: ...reply even if it waits for the specified time Initial value 0300H 768 symbols Set value 1H 1 symbol The ACKRCVWIT register consists of 16 bits and can be accessed serial interface communication in 8...

Page 635: ...ng retransmission Initial value 0004H 4 symbols Set value 1H 1 symbol The RETRNWUP register consists of 16 bits and can be accessed serial interface communication in 8 bit unit Reset signal generation...

Page 636: ...frame length value upon reception The value is stores at the timing when the packet data reception is started The value is retained until the start of the next packet data reception However the regist...

Page 637: ...length and the CRC length in 2 or 4 bytes for the frame length value Transmits data regardless of the transmit frame length value when the ACK auto reply function is enabled to automatically reply wit...

Page 638: ...terface in 8 bit units Reset signal generation sets this register to 36FC3BA0H Figure 18 66 Frequency Setting Register BBFREQ Format Caution Be sure to clear bits 30 and 31 to 0 For details see 18 7 2...

Page 639: ...ormat Address 00AEH to 00ACH After reset 0000F0H R W Symbol 23 22 21 20 19 18 17 16 BBSYMBL RATE SYMBLRATE 23 SYMBLRATE 22 SYMBLRATE 21 SYMBLRATE 20 SYMBLRATE 19 SYMBLRATE 18 SYMBLRATE 17 SYMBLRATE 16...

Page 640: ...transmit bit 2 is used to transmit bit 2 of the PHR upon transmission The interleaving enable bit is used to enable the interleaving Set INTERLEAVEEN bit to 1 to use FEC The BBSUBGCON register is set...

Page 641: ...on sets this register to 42H Figure 18 69 Modulation Method Setting Register BBMODSET Format Caution Be sure to clear bits 2 to 5 to 0 Address 00B1H After reset 42H R W Symbol 7 6 5 4 3 2 1 0 BBMODSET...

Page 642: ...p to 2000 symbols CCATIME register is set via serial interface in 8 bit units Reset signal generation sets this register to 000DH Figure 18 70 CCA Time Register CCATIME Format Caution The lower limit...

Page 643: ...led Setting 3 to 5 is available initial value is three times The ANTSELOUT pin status bit is used to indicate which ANTSELOUT pin is currently in the high level output state The BBANTDIV register is s...

Page 644: ...til when the next mode switch frame is received BBRXMODESW register is read via serial interface in 8 bit units Reset signal generation clears this register to 0000H Figure 18 73 Mode Switch Frame Rec...

Page 645: ...from the lower byte to the upper byte because the upper three bits are stored at the timing when the data of lower 8 bits is read BBTXCOUNT register is set via serial interface in 8 bit units Reset si...

Page 646: ...ame length value is stored The reading value is corresponding save bank specified by receive data save bank select bit The BBPHRRX register is read by the serial interface in 8 bit units Reset signal...

Page 647: ...its Set following values for each modification 2FSK 2GFSK 00007209H 4FSK 4GFSK BFAEAAEBH BBSFD register is read via serial interface in 8 bit units Reset signal generation sets this register to 000072...

Page 648: ...n by using the number of SFD setting bit 00 1 byte SFD setting register bits 7 to 0 01 2 bytes SFD setting register bits 15 to 0 10 Prohibited 11 4 bytes SFD setting register bits 31 to 0 The BBBSHRCO...

Page 649: ...at the high level The reading value is corresponding save bank specified by receive data save bank select bit The value is set as 2 s complement The setting unit is dBm ex 19EH is 98dBm BBANT1RD regi...

Page 650: ...ister is used to set the timeout value when there is no receive start operation after when exceeding the threshold value upon antenna diversity in operation The operation returns to the antenna select...

Page 651: ...ister is used to indicate the total number of count values of the back off period upon CSMA CA The maximum value of the count value is FFFFH BBBOPTOTAL register is set via serial interface in 8 bit un...

Page 652: ...the total number of count vales upon CSMA CA The maximum value of the count is FFH BBCCATOTAL register is set via serial interface in 8 bit units Reset signal generation clears this register to 00H Fi...

Page 653: ...etting register 02 after writing RF initial setting register 00 and 01 Caution Two bytes of RF initial setting register 00 and 01 must be written continuously SEN signal keeps low level RF initial set...

Page 654: ...etting register 12 after writing RF initial setting register 10 and 11 Caution Two bytes of RF initial setting register 10 and 11 must be written continuously SEN signal keeps low level RF initial set...

Page 655: ...er 1 BBPANID1 Format 76 Short address register 1 BBSHORTAD1 This register is used to set the short address of second address filter It consists of 16 bits and is used to detect the match with a receiv...

Page 656: ...0000H Figure 18 90 Extended Address Register 1 BBEXTENDAD10 to BBEXTENDAD13 Format Address 00EBH 00EAH After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 BBEXTEN DAD13 7 6 5 4 3 2 1 0 BBEXTENDAD13 Ext...

Page 657: ...is enabled This register consists of 12 bits BBTIMEOUT register is set via serial interface in 8 bit units Reset signal generation sets this register to 07D0H 07D0H 2 ms 1H 1 s Figure 18 91 Receive Ti...

Page 658: ...GPIO4 pin by using the ANTSW output enable bit ANTSWCON register is set via serial interface in 8 bit units Reset signal generation sets this register to 00H Figure 18 92 ANTSW Control Register ANTSW...

Page 659: ...d the clock output select bit 1 CLKOUTCON register is set via serial interface in 8 bit units Reset signal generation sets this register to 00H Figure 18 93 Clock Output Control Register CLKOUTCON For...

Page 660: ...to 00H Figure 18 94 Port Direction Register GPIODIR Format Caution Be sure to clear bits 5 to 7 to 0 Address 0082H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 GPIODIR 0 0 0 GPIO4DIR GPIO3DIR GPIO2DIR G...

Page 661: ...Reset signal generation clears this register to 00H Figure 18 95 Port Data Register GPIODATA Format Caution Be sure to clear bits 5 to 7 to 0 Bit 5 becomes X undefined when read out Address 0083H Aft...

Page 662: ...Reset signal generation sets this register to undefined BBSFD2 register is set via serial interface in 8 bit units Figure 18 96 SFD Setting Register 2 BBSFD2 Format Address 0103H 0100H After reset XXX...

Page 663: ...consists of 32 bits Reset signal generation sets this register to undefined BBSFD4 register is set via serial interface in 8 bit units Figure 18 98 SFD Setting Register 4 BBSFD4 Format Address 0107H...

Page 664: ...s used to set enable or disable of FEC in automatic ACK reply when FEC control bit for automatic ACK reply is set to 1 FEC control bit for automatic ACK reception is used to switch enable or disable c...

Page 665: ...KSFD 0 1 phyMRFSKSFD 1 FECEN ACKRCV FEC enable bit for automatic ACK reception 0 Disable 1 Enable FECCON ACKRCV FEC control bit for automatic ACK reception 0 Regardless of FEC enable bit for automatic...

Page 666: ...dress filter extension bit is enabled values of first and second address filter match monitor bits are invalid under the following conditions Frame version 00 01 Frame type Beacon frame No destination...

Page 667: ...save bank select bit ACK reply antenna switch invert bit is used to invert to receive antenna output as ACK reply antenna for automatic ACK reply BBANTDIV2 register is set via serial interface in 8 b...

Page 668: ...is error detected When the operation is under noisy environment usually no communication state is detected correctly adjusting this register The default is 1 no communication state is detected when t...

Page 669: ...pace accesses from MCU through serial communication The serial connection on the user board etc is not required since this serial interface is internally connected in RL78 G1H device Figure 18 103 sho...

Page 670: ...mode Transmission mode Transmission reception mode Transmission reception mode Master slave Only master is supported Slave Interrupt Selectable from the following types Transfer end interrupt in singl...

Page 671: ...munication format and Table 18 11 shows the description of the format Figure 18 104 Internal Serial Communication Format Cycle Access destination DO2 DI6 DI5 DI4 DI3 DO7 DO6 DO5 DO4 DO3 n nth byte Bas...

Page 672: ...dress at the access destination Bit 7 to Bit 3 in the 1st byte and 2nd byte R W 2 bit R W control Bit 2 and Bit 1 in the 2nd byte 00b Writes to the access destination 11b Reads from the access destina...

Page 673: ...al oscillator circuit are activated The settings and data of each register in the RF transceiver are retained Returns to IDLE after completion of operation in case of transmission Returns to IDLE afte...

Page 674: ...tion receive completion or CCA completion The following function is provided between TX and RX AUTO RX ACK reception function Changes to the reception state automatically via the IDLE state after data...

Page 675: ...ternal pin RFRESETB internal pin in this order Figure 18 107 shows the Wake Up operation RF unit startup sequence for the REFCLKIN_RF external clock TCXO etc input The high level is fixed in the OSCDR...

Page 676: ...MCU pins connected internally Table 18 12 Pin Status Pin SLEEP 1 2 3 IDLE SEN Internal pin Input Input Input Input Input SCLK Internal pin Input Input Input Input Input SIN Internal pin Input Input I...

Page 677: ...able 18 14 when to use the product Table 18 13 Description of Each State of Wake Up Operation State Description 1 Time taken from startup of the XTAL_RF oscillator circuit to the oscillation developme...

Page 678: ...8 04 0052 0E 0053 01 0054 5E 0057 50 0058 E6 005A F0 005C F0 0078 E6 007C 50 007E E6 0086 03 008E 73 0092 7B 0094 26 0096 73 00A6 0F 0402 04 0430 02 043A 94 046F 05 0470 05 0473 F6 0475 32 047A 60 047...

Page 679: ...pin to the low level and then set the OSCDRVSEL internal pin DON internal pin and RFRESETB internal pin to the low level respectively When using the REFCLKIN_RF external clock fix the OSCDRVSEL intern...

Page 680: ...ernal pin Low input High input High input High input RFRESETB internal pin Low input High input High input High input INTOUT Hi Z Operable Operable Operable CLKOUT Hi Z Operable Operation prohibited O...

Page 681: ...mode 5 Write in the transmission RAM Bank 0 0200H to 027FH address Bank 1 0280H to 02FFH address 6 Set the transmission frame length in the transmission frame length register BBTXFLEN 7 Set the TRNTRG...

Page 682: ...fier register 1 BBPANID1 5 Set the short address register 0 BBSHORTAD0 short address register 1 BBSHORTAD1 or extended address register 0 BBEXTENDAD00 to BBEXTENDAD03 extended address register 1 BBEXT...

Page 683: ...BBFREQ For details see 18 7 2 3 RF frequency setting for reception 3 For the beacon mode set the BEACON bit of the transmission reception mode register 0 BBTXRXMODE0 to 1 4 Set the BOFFPROD0 BOFFPROD7...

Page 684: ...according to the table and 25H to address 00DH Fix the data 7 5 at 000b 6 Set the data 7 4 of 00DCH address according to the table and 1AH to address 00DDH Fix the data 3 0 at 0000b Figure 18 108 to F...

Page 685: ...A 0 1F 6 28 2 1B 0 1F 6 29 2 1C 0 1F 6 30 2 1D 0 1F 6 31 2 1E 0 1F 6 32 2 1F 0 1F 6 33 3 05 1 15 6 34 3 06 1 15 6 35 3 07 1 15 6 36 3 08 1 15 6 37 3 09 1 15 6 38 3 0A 1 15 6 39 3 0B 1 15 6 40 3 0C 1 1...

Page 686: ...C 2 1F 6 66 3 0D 2 1F 6 67 3 0E 2 1F 6 68 3 0F 2 1F 6 69 3 10 2 1F 6 70 3 11 2 1F 6 71 3 12 2 1F 6 72 3 13 2 1F 6 73 3 14 2 1F 6 74 2 15 2 1F 6 75 2 16 2 1F 6 76 2 17 2 1F 6 77 2 18 2 1F 6 78 2 19 2 1...

Page 687: ...1D 7 15 6 99 1 1E 7 15 6 100 1 1E 8 11 6 101 1 1F 8 11 6 Table 18 19 Gain Set Frequency band identifier 9 3 3 Gain set 0090H address Bit 1 0 0092H address Bit 4 0 00DCH address Bit 4 0 00DDH address i...

Page 688: ...1F 7 2 3 01 0 1F 7 3 3 02 0 1F 7 4 3 03 0 1F 7 5 3 04 0 1F 7 6 3 05 0 1F 7 7 3 06 0 1F 7 8 3 07 0 1F 7 9 3 08 0 1F 7 10 3 09 0 1F 7 11 3 0A 0 1F 7 12 3 0B 0 1F 7 13 3 0C 0 1F 7 14 3 0D 0 1F 7 15 3 0E...

Page 689: ...7 42 3 0F 1 0F 7 43 3 10 1 0F 7 44 3 11 1 0F 7 45 3 12 1 0F 7 46 3 13 1 0F 7 47 3 14 1 0F 7 48 2 15 1 0F 7 49 2 16 1 0F 7 50 2 17 1 0F 7 51 2 18 1 0F 7 52 2 19 1 0F 7 53 2 1A 1 0F 7 54 2 1B 1 0F 7 55...

Page 690: ...DCH address Bit 4 0 00DDH address is set to 25H 00DCH address Bit 7 4 00DDH address is set to 1AH 80 3 11 3 1F 7 81 3 12 3 1F 7 82 3 13 3 1F 7 83 3 14 3 1F 7 84 3 11 4 1B 7 85 3 12 4 1B 7 86 3 13 4 1B...

Page 691: ...UH0575EJ0120 Rev 1 20 Page 673 of 920 Dec 22 2016 Figure 18 109 Relationship between Transmission Output Power and Gain Set 20 15 10 5 0 5 10 15 20 0 10 20 30 40 50 60 70 80 90 100110 Output power dBm...

Page 692: ...3 01 0 1F 6 3 3 02 0 1F 6 4 3 03 0 1F 6 5 3 04 0 1F 6 6 3 05 0 1F 6 7 3 06 0 1F 6 8 3 07 0 1F 6 9 3 08 0 1F 6 10 3 09 0 1F 6 11 3 0A 0 1F 6 12 3 0B 0 1F 6 13 3 0C 0 1F 6 14 3 0D 0 1F 6 15 3 0E 0 1F 6...

Page 693: ...5 6 43 3 0F 1 15 6 44 3 10 1 15 6 45 3 11 1 15 6 46 3 12 1 15 6 47 3 13 1 15 6 48 3 14 1 15 6 49 2 15 1 15 6 50 2 16 1 15 6 51 2 17 1 15 6 52 2 18 1 15 6 53 2 19 1 15 6 54 2 1A 1 15 6 55 2 1B 1 15 6 5...

Page 694: ...dress Bit 4 0 00DDH address is set to 25 00DCH address Bit 7 4 00DDH address is set to 1AH 81 2 1B 2 1F 6 82 2 1C 2 1F 6 83 2 1D 2 1F 6 84 2 1E 2 1F 6 85 2 1F 2 1F 6 86 3 11 4 16 6 87 3 12 4 16 6 88 3...

Page 695: ...UH0575EJ0120 Rev 1 20 Page 677 of 920 Dec 22 2016 Figure 18 110 Relationship between Transmission Output Power and Gain Set 20 15 10 5 0 5 10 15 20 0 10 20 30 40 50 60 70 80 90 100110 Output power dBm...

Page 696: ...01 0 1F 6 3 3 02 0 1F 6 4 3 03 0 1F 6 5 3 04 0 1F 6 6 3 05 0 1F 6 7 3 06 0 1F 6 8 3 07 0 1F 6 9 3 08 0 1F 6 10 3 09 0 1F 6 11 3 0A 0 1F 6 12 3 0B 0 1F 6 13 3 0C 0 1F 6 14 3 0D 0 1F 6 15 3 0E 0 1F 6 1...

Page 697: ...43 3 0F 1 15 6 44 3 10 1 15 6 45 3 11 1 15 6 46 3 12 1 15 6 47 3 13 1 15 6 48 3 14 1 15 6 49 2 15 1 15 6 50 2 16 1 15 6 51 2 17 1 15 6 52 2 18 1 15 6 53 2 19 1 15 6 54 2 1A 1 15 6 55 2 1B 1 15 6 56 2...

Page 698: ...to 19 00DCH address Bit 4 0 00DDH address is set to 25 00DCH address Bit 7 4 00DDH address is set to 1AH 81 2 1D 2 1F 6 82 2 1E 2 1F 6 83 2 1F 2 1F 6 84 3 11 4 16 6 85 3 12 4 16 6 86 3 13 4 16 6 87 3...

Page 699: ...f the frequency setting is integer times N 864 MHz 912 MHz of XIN frequency 48 MHz the transmission character will degrade If the frequency matches the following condition it must be changed to other...

Page 700: ...2 Set the data 7 0 of 0095H address following to the Table 18 29 to 18 50 according to the RF frequency of reception 3 Set data of 0095H address in IDLE mode 4 Frequencies 864 MHz 400 kHz and 912 MHz...

Page 701: ...ower limit RF frequency MHz Upper limit RF frequency MHz 0095H address Bit 7 0 1 863 0000 863 5875 8H 2 863 6000 864 4000 Prohibited 3 864 4125 865 7125 8H 4 865 7250 865 9750 48H 5 865 9875 866 2750...

Page 702: ...7 899 7875 899 8125 28H 8 899 8250 899 9750 8H 9 899 9875 900 0125 28H 10 900 0250 900 1750 8H 11 900 1875 900 2125 28H 12 900 2250 901 0000 8H Table 18 33 RF Frequency Set Frequency band identifier 5...

Page 703: ...48H 12 900 0750 900 7250 8H 13 900 7375 900 8375 28H 14 900 8500 901 0000 8H Table 18 35 RF Frequency Set Frequency band identifier 6 Mode 007 RF frequency set Lower limit RF frequency MHz Upper limi...

Page 704: ...906 1375 28H 6 906 1500 907 8500 8H 7 907 8625 908 1375 28H 8 908 1500 909 8500 8H 9 909 8625 910 1375 28H 10 910 1500 911 5875 8H 11 911 6000 912 4000 Prohibited 12 912 4125 913 8500 8H 13 913 8625...

Page 705: ...8 0375 28H 8 908 0500 908 2625 48H 9 908 2750 909 7250 8H 10 909 7375 910 0375 28H 11 910 0500 910 2625 48H 12 910 2750 911 5875 8H 13 911 6000 912 4000 Prohibited 14 912 4125 913 7250 8H 15 913 7375...

Page 706: ...2125 48H 11 908 2250 908 3500 68H 12 908 3625 909 6375 8H 13 909 6500 909 9500 28H 14 909 9625 910 2125 48H 15 910 2250 911 5875 8H 16 911 6000 912 4000 Prohibited 17 912 4125 913 7750 8H 18 913 7875...

Page 707: ...H 4 919 7375 920 2625 28H 5 920 2750 921 7250 8H 6 921 7375 922 2625 28H 7 922 2750 923 5000 8H Table 18 43 RF Frequency Set Frequency band identifier 8 Mode 015 RF frequency set Lower limit RF freque...

Page 708: ...25 7125 8H 7 925 7250 926 2750 28H 8 926 2875 927 7125 8H 9 927 7250 928 0000 28H Table 18 46 RF Frequency Set Frequency band identifier 9 Mode 017 RF frequency set Lower limit RF frequency MHz Upper...

Page 709: ...23 5625 924 4750 28H 8 924 4875 925 5125 8H 9 925 5250 926 2750 28H 10 926 2875 926 4750 48H 11 926 4875 927 5125 8H 12 927 5250 928 0000 28H Table 18 48 RF Frequency Set Frequency band identifier Oth...

Page 710: ...908 1250 28H 8 908 1375 908 1750 48H 9 908 1875 909 8125 8H 10 909 8250 910 1250 28H 11 910 1375 910 1750 48H 12 910 1875 911 5875 8H 13 911 6000 912 4000 Prohibited 14 912 4125 913 8125 8H 15 913 825...

Page 711: ...8 5250 68H 14 908 5375 909 4625 8H 15 909 4750 909 7750 28H 16 909 7875 910 0375 48H 17 910 0500 911 5875 8H 18 911 6000 912 4000 Prohibited 19 912 4125 913 9500 8H 20 913 9625 914 2125 48H 21 914 225...

Page 712: ...Each Data Rate List Frequency band identifier PHY Frequency band MHz Modulation Mode Data rate kbps Modulation index Channel spacing kHz 4 863 MHz Europe 863 to 870 2FSK 2GFSK 001 50 1 200 002 100 400...

Page 713: ...C 0C B0 04 01 0C 0C 006 40 A3 02 0C 0C 58 02 01 0C 0C 6 901 MHz US 007 10 A3 02 0C 0C 60 09 00 0C 0C 008 20 A3 02 0C 0C B0 04 00 0C 0C 009 40 A3 02 0C 0C 58 02 01 0C 0C 7 915 MHz US 010 50 A3 42 0C 0C...

Page 714: ...006 40 8B 93 AA 09 72 00 00 8B 93 02 6 901 MHz US 007 10 83 8B AA 09 72 00 00 83 8B 02 008 20 87 8F AA 09 72 00 00 87 8F 02 009 40 8B 93 AA 09 72 00 00 8B 93 02 7 915 MHz US 010 50 8C 94 AA 09 72 00...

Page 715: ...21 00 02 09 006 40 96 1E 1E 0C 1E E6 40 00 03 09 6 901 MHz US 007 10 90 06 0A 08 78 73 B7 00 01 09 008 20 96 3C 3C 0C 3C 91 21 00 02 09 009 40 96 1E 1E 0C 1E E6 40 00 03 09 7 915 MHz US 010 50 96 0B 0...

Page 716: ...32 00 6 901 MHz US 007 10 09 28 02 A6 1B 0F 34 00 09 02 00 008 20 09 28 02 A6 1A 0F 34 00 03 32 00 009 40 09 28 02 A6 1A 0F 34 00 03 32 00 7 915 MHz US 010 50 01 28 02 A6 1B 0F 34 00 3B 55 05 011 150...

Page 717: ...FF 3F 6 901 MHz US 007 10 46 66 20 55 20 55 05 30 FF FF 3F 008 20 46 55 20 55 20 55 00 30 FF FF 3F 009 40 46 55 20 55 20 55 1C 2B FF FF 3F 7 915 MHz US 010 50 46 66 20 55 20 55 12 26 FF FF 3F 011 150...

Page 718: ...F6 72 6 901 MHz US 007 10 FF 3F 10 04 38 48 04 F1 36 F6 72 008 20 FF 3F 10 04 38 48 04 F1 36 F6 72 009 40 FF 3F 10 04 38 48 04 F1 36 F6 72 7 915 MHz US 010 50 FF 3F 10 10 00 48 04 00 36 F6 72 011 150...

Page 719: ...00 11 6 901 MHz US 007 10 00 00 5E 70 00 00 C6 B4 00 00 10 008 20 00 00 5E 70 00 00 C6 B4 00 00 10 009 40 00 00 5E 70 00 00 C6 B4 00 00 11 7 915 MHz US 010 50 00 00 5E 70 00 00 C6 B4 00 00 11 011 150...

Page 720: ...0A 63 6 901 MHz US 007 10 0E 10 23 06 0A 5F 0D CA CA 0A 63 008 20 0E 10 23 06 0A 5F 0D CA CA 0A 63 009 40 0E 10 23 06 0A 5F 0D CA CA 0A 63 7 915 MHz US 010 50 0E 10 23 06 0A 5F 0D BA BA 0A 63 011 150...

Page 721: ...20 Note 1 01H Note 2 02H Note 3 0BH 006 40 Note 1 01H Note 2 02H Note 3 0BH 6 901 MHz US 007 10 Note 1 01H Note 2 02H Note 3 0BH 008 20 Note 1 01H Note 2 02H Note 3 0BH 009 40 Note 1 01H Note 2 02H N...

Page 722: ...smission mode 18 8 2 Cautions on First and Second Address Filter Match Monitor Bits 1 When the address filter extension bit is disabled values of first and second address filter match monitor bits are...

Page 723: ...or more interrupt requests each having the same priority are simultaneously generated then they are processed according to the default priority of vectored interrupt servicing Default priority see Tab...

Page 724: ...CSI21 CSI21 transfer end or buffer empty interrupt 0016H 10 INTTM11H End of timer channel 11 count or capture at higher 8 bit timer operation 0018H 13 INTTM01H End of timer channel 01 count or capture...

Page 725: ...ote 1 Interrupt Source Internal External Vector Table Address Basic Configuration Type Note 2 Name Trigger Maskable 29 INTTM10 End of timer channel 10 count or capture Internal 0042H A 30 INTTM11 End...

Page 726: ...riority flag 1 MK Interrupt mask flag PR0 Priority specification flag 0 PR1 Priority specification flag 1 C Software interrupt Internal bus Priority controller Vector table address generator IF Interr...

Page 727: ...registers EGN0 EGN1 Program status word PSW Tables 19 3 to 19 5 show a list of interrupt request flags interrupt mask flags and priority specification flags corresponding to interrupt request sources...

Page 728: ...upport these two interrupt sources Note 4 If one of the interrupt sources INTST3 and INTCSI30 is generated bit 4 of the IF1H register is set to 1 Bit 4 of the MK1H PR01H and PR11H registers supports t...

Page 729: ...TM13H is generated bit 4 of the IF2H register is set to 1 Bit 4 of the MK2H PR02H and PR12H registers support these two interrupt sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Pr...

Page 730: ...are combined to form 16 bit registers IF0 IF1 and IF2 they can be set by a 16 bit memory manipulation instruction Reset signal generation clears these registers to 00H Remark If an instruction that w...

Page 731: ...1 IF0L 0 because the compiled assembler must be a 1 bit memory manipulation instruction CLR1 If a program is described in C language using an 8 bit memory manipulation instruction such as IF0L 0xfe an...

Page 732: ...ese registers to FFH Remark If an instruction that writes data to this register is executed the number of instruction execution clocks increases by 2 clocks Figure 19 4 Format of Interrupt Mask Flag R...

Page 733: ...isters and bits differ depending on the product For details about the registers and bits available for each product see Tables 19 3 to 19 5 Be sure to set bits that are not available to the initial va...

Page 734: ...registers PR00 PR01 PR02 PR10 PR11 and PR12 they can be set by a 16 bit memory manipulation instruction Reset signal generation sets these registers to FFH Remark If an instruction that writes data to...

Page 735: ...FFH R W Symbol 7 6 5 4 3 2 1 0 PR01H TMPR010 TRJPR00 SRPR03 STPR03 CSIPR030 1 ITPR0 RTCPR0 ADPR0 Address FFFEFH After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR11H TMPR110 TRJPR10 SRPR13 STPR13 CSIPR130...

Page 736: ...at of External Interrupt Rising Edge Enable Registers EGP0 EGP1 and External Interrupt Falling Edge Enable Registers EGN0 EGN1 Address FFF38H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGP0 EGP7 EGP6...

Page 737: ...o the output mode the INTPn interrupt might be generated upon detection of a valid edge When switching the input port pins to the output mode set the port mode register PMxx to 0 after disabling the e...

Page 738: ...request if the value of the priority specification flag register of the acknowledged interrupt is not 00 its value minus 1 is transferred to the ISP0 and ISP1 flags The PSW contents are also saved int...

Page 739: ...Remark 1 clock 1 fCLK fCLK CPU clock If two or more maskable interrupt requests are generated simultaneously the request with a higher priority level specified in the priority specification flag is ac...

Page 740: ...interrupt currently being serviced see Figure 19 9 Note For the default priority refer to Tables 19 1 and 19 2 Interrupt Source List Start IF 1 MK 0 IE 1 Yes No Yes interrupt request generation Yes No...

Page 741: ...est Acknowledgment Timing Maximum Time Remark 1 clock 1 fCLK fCLK CPU clock 9 clocks Instruction CPU processing xxIF 6 clocks PSW and PC saved jump to interrupt servicing Interrupt servicing program I...

Page 742: ...ing to enable interrupt acknowledgment Moreover even if interrupts are enabled multiple interrupt servicing may not be enabled this being subject to interrupt priority control Two types of priority co...

Page 743: ...s enabled Remark 4 PR is a flag contained in the PR00L PR00H PR01L PR01H PR02L PR02H PR10L PR10H PR11L PR11H PR12L and PR12H registers PR 00 Specify level 0 with PR1 0 PR0 0 higher priority level PR 0...

Page 744: ...ed because its priority is lower than that of INTxx and multiple interrupt servicing does not take place The INTyy interrupt request is held pending and is acknowledged following execution of one main...

Page 745: ...rupt servicing does not take place The INTyy interrupt request is held pending and is acknowledged following execution of one main processing instruction PR 00 Specify level 0 with xxPR1x 0 xxPR0x 0 h...

Page 746: ...rated while the DIVHU DIVWU instruction is executed the instruction is suspended After the instruction is suspended the PC indicates the next instruction after DIVHU DIVWU An interrupt is generated by...

Page 747: ...owing compilers when DIVHU and DIVWU instructions are output at building NOP instruction is automatically inserted right after the output CA78K0R compiler product manufactured by Renesas Electronics C...

Page 748: ...bit CLR1 PSW bit RETB RETI POP PSW BTCLR PSW bit addr20 EI DI SKC SKNC SKZ SKNZ SKH SKNH MULHU MULH MACHU MACH Write instructions for the IF0L IF0H IF1L IF1H IF2L IF2H MK0L MK0H MK1L MK1H MK2L MK2H PR...

Page 749: ...oscillator and high speed on chip oscillator stop stopping the whole system thereby considerably reducing the CPU operating current Because this mode can be cleared by an interrupt request it enables...

Page 750: ...ontrolling A D Converter Caution 4 The following sequence is recommended for operating current reduction of the A D converter when the standby function is used First clear bit 7 ADCS and bit 0 ADCE of...

Page 751: ...e the setting was the high speed system clock high speed on chip oscillator clock or subsystem clock The operating statuses in the HALT mode are shown below Caution Because the interrupt request signa...

Page 752: ...lock fXT Status before HALT mode was set is retained fEXS Low speed on chip oscillator clock fIL Set by bits 0 WDSTBYON and 4 WDTON of option byte 000C0H and WUTMMCK0 bit of subsystem clock supply mod...

Page 753: ...TMMCK0 0 WDTON 1 and WDSTBYON 1 Oscillates WUTMMCK0 0 WDTON 1 and WDSTBYON 0 Stops CPU Operation stopped Code flash memory Data flash memory RAM Operation stopped Operable while in the DTC is executed...

Page 754: ...igure 19 1 Basic Configuration of Interrupt Function Note 2 Wait time for HALT mode release When vectored interrupt servicing is carried out Main system clock 15 to 16 clocks Subsystem clock RTCLPC 0...

Page 755: ...CHAPTER 21 RESET FUNCTION HALT instruction High speed on chip oscillator clock Oscillates Oscillation stopped Oscillates Wait for oscillation accuracy stabilization Status of CPU Reset signal Normal...

Page 756: ...essing is enabled and the interrupt request flag is 1 the interrupt request signal is generated the STOP mode is immediately cleared if set when the STOP instruction is executed in such a situation Ac...

Page 757: ...ops CPU Operation stopped Code flash memory Data flash memory RAM Port latch Status before STOP mode was set is retained Timer array unit Operation disabled Real time clock RTC Operable 12 bit Interva...

Page 758: ...Wait When vectored interrupt servicing is carried out 7 clocks When vectored interrupt servicing is not carried out 1 clock Caution To shorten oscillation stabilization time after the STOP mode is re...

Page 759: ...not carried out 1 clock Caution To reduce the oscillation stabilization time after release from the STOP mode while CPU operates based on the high speed system clock X1 oscillation switch the clock to...

Page 760: ...TION Status of CPU STOP instruction Wait for oscillation accuracy stabilization Oscillates Oscillation stopped Oscillation stopped Oscillates Normal operation high speed on chip oscillator clock STOP...

Page 761: ...be used During STOP mode detecting DTC activation by interrupt enables DTC transit to SNOOZE mode automatically For details see 16 3 Registers Controlling DTC In SNOOZE mode transition wait status to...

Page 762: ...ON 0 Stops CPU Operation stopped Code flash memory Data flash memory RAM Operation stopped Operable while in the DTC is executed Port latch Use of the status while in the STOP mode continues Timer arr...

Page 763: ...lease signal see Figure 19 1 Note 2 Transition time from STOP mode to SNOOZE mode Note 3 Enable the SNOOZE mode AWC 1 or SWC 1 immediately before switching to the STOP mode Remark For details of the S...

Page 764: ...al instruction is generated when instruction code FFH is executed Reset by the illegal instruction execution not issued by emulation with the in circuit emulator or on chip debug emulator Caution 1 Fo...

Page 765: ...S Voltage detection level register Internal bus Reset control flag register RESF Watchdog timer reset signal Reset signal TRAP WDTRF RPERF IAWRF LVIRF Set Clear Set Set Set Set Clear Clear Clear Clear...

Page 766: ...ection of RAM Parity Error or Detection of Illegal Memory Access Notes and Caution are listed on the next page Hi Z Note 3 Normal operation CPU status Reset period Note 1 High speed on chip oscillator...

Page 767: ...is in use 0 259 ms TYP 0 362 ms MAX when the LVD is off After power is supplied a voltage stabilization waiting time of about 0 99 ms TYP and up to 2 30 ms MAX is required before reset processing sta...

Page 768: ...ort mode fEX Clock input invalid the pin is input port mode Subsystem clock fXT Operation stopped the XT1 and XT2 pins are input port mode fEXS Clock input invalid the pin is input port mode fIL Opera...

Page 769: ...state of the special function register SFR after receiving a reset signal see 4 1 4 Special function register SFR area and 4 1 5 Extended special function register 2nd SFR 2nd Special Function Regist...

Page 770: ...Caution 2 When enabling RAM parity error resets RPERDIS 0 be sure to initialize the used RAM area at data access or the used RAM area 10 bytes at execution of instruction from the RAM area Reset gene...

Page 771: ...the procedure for checking a reset source Table 21 3 RESF Register Status When Reset Request Is Generated Reset Source Flag RESET Input Reset by POR Reset by Execution of Illegal Instruction Reset by...

Page 772: ...e detector generated Power on reset external reset generated WDTRF of RESF register 1 No LVIRF of RESF register 1 Yes No Internal reset request by the RAM parity error generated RPERF of RESF register...

Page 773: ...age falls below the range defined in 31 4 AC Characteristics When restarting the operation make sure that the operation voltage has returned within the range of operation Caution If an internal reset...

Page 774: ...The block diagram of the power on reset circuit is shown in Figure 22 1 Figure 22 1 Block Diagram of Power on reset Circuit 22 3 Operation of Power on reset Circuit The timing of generation of the in...

Page 775: ...n use 0 259 ms TYP 0 362 ms MAX when the LVD is off Note 5 After power is supplied the reset state must be retained until the operating voltage becomes in the range defined in 31 4 AC Characteristics...

Page 776: ...ge detection level VLVDH or higher without falling below the low voltage detection level VLVDL Note 4 The time until normal operation starts includes the following LVD reset processing time after the...

Page 777: ...supply voltage is then restored after an internal reset is generated only by the voltage detector LVD the following LVD reset processing time is required after the LVD detection level VLVD is reached...

Page 778: ...ption byte 000C1H The high voltage detection level VLVDH is used for releasing resets and generating interrupts The low voltage detection level VLVDL is used for generating resets b Reset mode option...

Page 779: ...Voltage Detector The voltage detector is controlled by the following registers Voltage detection register LVIM Voltage detection level register LVIS LVIOMSK Reference voltage source Internal bus Volt...

Page 780: ...LVIOMSK bit is only automatically set to 1 when the interrupt reset mode is selected option byte LVIMDS1 LVIMDS0 1 0 and reset or interrupt by LVD is masked Period during LVISEN 1 Waiting period from...

Page 781: ...LVIMDS0 1 1 81H When option byte LVIMDS1 LVIMDS0 0 1 01H Note 2 Writing 0 can only be allowed in the interrupt reset mode option byte LVIMDS1 LVIMDS0 1 0 Do not set LVIMD and LVILV in other cases The...

Page 782: ...alue of the voltage detection level select register LVIS is set to 81H Bit 7 LVIMD is 1 reset mode Bit 0 LVILV is 1 low voltage detection level VLVD Operation in LVD reset mode In the reset mode optio...

Page 783: ...LVIMDS0 1 1 Remark VPOR POR power supply rise detection voltage VPDR POR power supply fall detection voltage H H Time LVIF flag LVIMD flag LVIRF flag RESF register LVILV flag Internal reset signal PO...

Page 784: ...MDS0 0 and 1 in the option byte the state of an internal reset by the LVD is retained immediately after a reset until the supply voltage VDD exceeds the voltage detection level VLVD The LVD internal r...

Page 785: ...signal before the voltage falls below the operating voltage range defined in 31 4 AC Characteristics When restarting the operation make sure that the operation voltage has returned within the range of...

Page 786: ...until the supply voltage VDD exceeds the high voltage detection level VLVDH after power is supplied The internal reset is released when the supply voltage VDD exceeds the high voltage detection level...

Page 787: ...VDH clear LVIMD bit to 0 and the MCU shift to normal operation LVIF flag LVIOMSK flag Operation status LVIIF flag INTLVI LVIMD flag LVIRF flag LVILV flag Internal reset signal POR reset signal LVD res...

Page 788: ...ag is set to 1 by reset signal generation Note 2 After an interrupt is generated perform the processing according to Figure 23 8 Setting Procedure for Operating Voltage Check and Reset in interrupt an...

Page 789: ...OR reset signal LVD reset signal Supply voltage VDD VLVDL VPOR 1 51 V TYP VPDR 1 50 V TYP VLVDH LVIMK flag set by software LVISEN flag set by software Save processing RESET Normal operation RESET Norm...

Page 790: ...supply fall detection voltage Figure 23 8 Setting Procedure for Operating Voltage Check and Reset INTLVI generated No Save processing LVISEN 1 Perform required save processing LVILV 0 LVIOMSK 0 No LV...

Page 791: ...f each system by means of a software counter that uses a timer and then initialize the ports Figure 23 9 Example of Software Processing If Supply Voltage Fluctuation is 50 ms or Less in Vicinity of LV...

Page 792: ...reset input a low level for 10 s or more to the RESET pin To perform an external reset upon power application input a low level to the RESET pin turn power on continue to input a low level to the pin...

Page 793: ...etection function This detects parity errors when the RAM is read as data 3 RAM guard function This prevents RAM data from being rewritten when the CPU freezes 4 SFR guard function This prevents SFRs...

Page 794: ...er time The CRC generator polynomial used complies with X16 X12 X5 1 of CRC 16 CCITT The high speed CRC operates in MSB first order from bit 31 to bit 0 Caution The CRC operation result might differ d...

Page 795: ...0 0 1 1 00000H to 0FFFBH 64K 4 bytes 0 0 0 1 0 0 00000H to 13FFBH 80K 4 bytes 0 0 0 1 0 1 00000H to 17FFBH 96K 4 bytes 0 0 0 1 1 0 00000H to 1BFFBH 112K 4 bytes 0 0 0 1 1 1 00000H to 1FFFBH 128K 4 byt...

Page 796: ...2 Format of Flash memory CRC operation result register PGCRCL Caution The PGCRCL register can only be written if CRC0EN bit 7 of the CRC0CTL register 1 Figure 24 3 shows the Flowchart of Flash Memory...

Page 797: ...t value in the lowest 4 bytes CRC operation range setting Set FEA5 to FEA0 bits PGCRCL 0000H All xxMKx 1 Copied to RAM to HALT instruction and RET instruction initialize 10 bytes CRC0EN 1 CALL instruc...

Page 798: ...mial used is X16 X12 X5 1 of CRC 16 CCITT The data to be input is inverted in bit order and then calculated to allow for LSB first communication For example if the data 12345678H is sent from the LSB...

Page 799: ...to set the CRC operation data of general purpose CRC The possible setting range is 00H to FFH The CRCIN register can be set by an 8 bit memory manipulation instruction Reset signal generation clears t...

Page 800: ...Read the value written to CRCD register before writing to CRCIN register Caution 2 If writing and storing operation result to CRCD register conflict the writing is ignored Operation flow Figure 24 6...

Page 801: ...access is to proceed before reading data The RL78 s CPU executes look ahead due to the pipeline operation the CPU might read an uninitialized RAM area that is allocated beyond the RAM used which cause...

Page 802: ...for details on how to confirm internal resets due to RAM parity errors Confirm that a parity error has occurred RPERF 1 Note No RAM check Parity error has occurred RPERDIS 1 RAM check RPEF 1 RPERDIS...

Page 803: ...r is used to control the detection of invalid memory access and RAM SFR guard function GRAM1 and GRAM0 bits are used in RAM guard function The IAWCTL register can be set by an 8 bit memory manipulatio...

Page 804: ...e 24 10 Format of Invalid memory access detection control register IAWCTL Note Pxx Port register is not guarded Address F0078H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IAWCTL IAWEN 0 GRAM1 GRAM0 0 G...

Page 805: ...ucts Code Flash Memory 00000H to xxxxxH RAM zzzzzH to FFEFFH Lowest Detection Address yyyyyH when Reading Fetching Executing Instructions R5F11FLJ 262144 8 bits 00000H to 3FFFFH 24576 8 bit F9F00H to...

Page 806: ...ation clears this register to 00H Figure 24 12 Format of Invalid memory access detection control register IAWCTL Note Only writing 1 to the IAWEN bit is enabled not writing 0 to it after setting it to...

Page 807: ...rdware clock frequency fCLK High speed on chip oscillator clock fIH High speed system clock fMX 2 Input to channel 1 of the timer array unit 0 Timer input to channel 1 TI01 Low speed on chip oscillato...

Page 808: ...lears this register to 00H Figure 24 14 Format of Timer input select register 0 TIS0 Address F0074H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 TIS0 0 0 0 TIS04 0 TIS02 TIS01 TIS00 TIS04 Selection of t...

Page 809: ...t 2 1 5 Select the ANIx pin as the target for A D conversion by setting the ADTES register ADTES1 ADTES0 0 0 6 Perform A D conversion for the ANIx pin conversion result 1 2 7 Select the positive refer...

Page 810: ...Rev 1 20 Page 792 of 920 Dec 22 2016 Figure 24 15 Configuration of A D Test Function ANI0 AVREFP ANI1 AVREFM ANIxx ANIxx VDD VSS A D convertor side reference voltage A D convertor side reference volta...

Page 811: ...ve reference voltage as the target of A D conversion when measuring the full scale The ADTES register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this registe...

Page 812: ...M15 Caution 3 Do not use the ADS register to set ports that to be set as digital I O using the A D port configuration register ADPC Caution 4 Do not use the ADS register to set ports that to be set as...

Page 813: ...vel when the pin is output mode in which PMmn bit of port mode register PMm is 0 This register can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears these regis...

Page 814: ...t voltage see Table 25 1 Note When it shifts to the subsystem clock operation or STOP mode during the on chip debugging the regulator output voltage is kept at 2 1 V not decline to 1 8 V Table 25 1 Re...

Page 815: ...ation in the HALT or STOP mode Setting of interval time of watchdog timer Setting of window open period of watchdog timer Setting of interval interrupt of watchdog timer Interval interrupt is used or...

Page 816: ...the boot swap operation is used because 000C2H is replaced by 010C2H 26 1 2 On chip debug option byte 000C3H 010C3H Control of on chip debug operation On chip debug operation is disabled or enabled Ha...

Page 817: ...erval interrupt is not used 1 Interval interrupt is generated when 75 1 2 fIL of the overflow time is reached WINDOW1 WINDOW0 Watchdog timer window open period Note 2 0 0 Setting prohibited 0 1 50 1 0...

Page 818: ...on voltage is a typical value For details see 31 6 3 LVD characteristics WDCS2 WDCS1 WDCS0 Watchdog timer overflow time fIL 17 25 kHz MAX Period over which clearing the counter is prohibited when the...

Page 819: ...Remark 2 The detection voltage is a typical value For details see 31 6 3 LVD characteristics Address 000C1H 010C1H Note 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0 Detection volta...

Page 820: ...OR Remark 2 The detection voltage is a typical value For details see 31 6 3 LVD characteristics Address 000C1H 010C1H Note 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0 Detection vol...

Page 821: ...gnal After the power supply is turned off this LSI should be placed in the STOP mode or placed in the reset state by utilizing the voltage detection circuit or controlling the externally input reset s...

Page 822: ...or details Address 000C2H 010C2H Note 7 6 5 4 3 2 1 0 CMODE1 CMODE0 1 0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 CMODE1 CMODE0 Setting of flash operation mode Operating Frequency Range Operating Voltage Range...

Page 823: ...to 1 Remark The value on bits 3 to 1 will be written over when the on chip debug function is in use and thus it will become unstable after the setting However be sure to set the default values 0 1 an...

Page 824: ...e The code flash memory can be rewritten to through serial programming using a flash memory programmer or an external device UART communication or through self programming Serial Programming Using Fla...

Page 825: ...oard programming Data can be written to the flash memory with a dedicated program adapter FA series before the RL78 microcontroller is mounted on the target system Remark FL PR5 and FA series are prod...

Page 826: ...nication between the dedicated flash memory programmer and the RL78 microcontroller is established by serial communication using the TOOL0 pin via a dedicated single line UART of the RL78 microcontrol...

Page 827: ...details Note Connect REGC pin to ground via a capacitor 0 47 to 1 F Table 27 2 Pin Connection Dedicated Flash Memory Programmer RL78 G1H Signal Name I O Pin Function Pin Name PG FP5 FL PR5 E1 on chip...

Page 828: ...put pin When this pin is used via pull down resistors use the 500 k or more resistors Remark 1 tHD How long to keep the TOOL0 pin at the low level from when the external and internal resets end for se...

Page 829: ...characteristics since it is used to stabilize internal voltage 27 2 5 X1 and X2 pins Connect X1 and X2 in the same status as in the normal operation mode Remark In the flash memory programming mode th...

Page 830: ...3 1 Serial programming procedure The following figure illustrates a flow for rewriting the code flash memory through serial programming Figure 27 4 Code Flash Memory Manipulation Procedure Start End...

Page 831: ...tion Application Note R01AN0815 Figure 27 5 Setting of Flash Memory Programming Mode 1 The low level is input to the TOOL0 pin 2 The external reset ends POR and LVD reset must end before the external...

Page 832: ...ions on writing erasing or verification Remark 2 For details about communication commands see 27 3 4 Communication commands Table 27 4 Programming Modes and Voltages at Which Data Can Be Written Erase...

Page 833: ...ry programmer Note 2 Because factors other than the baud rate error such as the signal waveform slew also affect UART communication thoroughly evaluate the slew as well as the baud rate error Table 27...

Page 834: ...from the programmer Erase Block Erase Erases a specified area in the flash memory Blank check Block Blank Check Checks if a specified block in the flash memory has been correctly erased Write Program...

Page 835: ...7 8 Processing Time for Each Command When PG FP5 Is in Use Reference Value Remark The command processing times reference values shown in the table are typical values under the following conditions Por...

Page 836: ...self programming If it is kept stopped it should be operated HIOSTOP 0 The flash self programming library should be executed after 30 s have elapsed Remark 1 For details of the self programming funct...

Page 837: ...e flash memory by using a flash self programming library Figure 27 6 Flow of Self Programming Rewriting Flash Memory Initialize flash environment Code flash memory control start Flash shield window se...

Page 838: ...he original boot program area boot cluster 0 As a result even if a power failure occurs while the area is being rewritten the program is executed correctly because it is booted from boot cluster 1 to...

Page 839: ...gram 3 2 1 0 7 6 5 4 00000H 01000H 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 00000H 01000H Writing blocks 4 to 7 Erasing block 4 Erasing block 5 W...

Page 840: ...w can only be used for the code flash memory and is not supported for the data flash memory Remark See 27 6 Security Settings to prohibit writing erasing during serial programming Table 27 9 Relations...

Page 841: ...written by means of self programming After the setting of prohibition of writing is specified releasing the setting by the Security Release command is enabled by a reset Disabling rewriting boot clust...

Page 842: ...cks cannot be erased Can be performed Note Prohibition of writing Blocks can be erased Cannot be performed Prohibition of rewriting boot cluster 0 Boot cluster 0 cannot be erased Boot cluster 0 cannot...

Page 843: ...data flash memory that is background operation BGO is supported Because the data flash memory is an area exclusively used for data it cannot be used to execute instructions Accessing the data flash m...

Page 844: ...h The DFLCTL register is set by a 1 bit or 8 bit memory manipulation instruction Reset input sets this register to 00H Figure 27 10 Format of Data flash control register DFLCTL Caution Manipulating th...

Page 845: ...r each main clock mode Setup time for each main clock mode HS High speed main 5 s LS Low speed main 720 ns 3 After the wait the data flash memory can be accessed Caution 1 Accessing the data flash mem...

Page 846: ...f the flash memory may be exceeded when this function is used and product reliability therefore cannot be guaranteed Renesas Electronics is not liable for problems occurring when the on chip debug fun...

Page 847: ...ing of User Resources To perform communication between the RL78 microcontroller and E1 on chip debugging emulator as well as each debug function the securing of memory space must be done beforehand If...

Page 848: ...he address of this area varies depending on the stack increase and decrease That is 4 extra bytes are consumed for the stack area used When using self programming 12 extra bytes are consumed for the s...

Page 849: ...by BCD Correction Circuit The BCD correction circuit uses the following registers BCD correction result register BCDADJ 29 2 1 BCD correction result register BCDADJ The BCDADJ register stores correcti...

Page 850: ...ster correction value and the correction result is stored in the A register and CY flag Caution The value read from the BCDADJ register varies depending on the value of the A register when it is read...

Page 851: ...d by subtracting the value of the BCDADJ register correction value from the A register subtraction result in binary in binary and the correction result is stored in the A register and CY flag Caution...

Page 852: ...Page 834 of 920 Dec 22 2016 CHAPTER 30 INSTRUCTION SET This chapter lists the instructions in the RL78 microcontroller instruction set For details of each operation and operation code refer to the se...

Page 853: ...ses in the table below R0 R1 R2 etc can be used for description Note Bit 0 0 when an odd address is specified Remark The special function registers can be described to operand sfr as symbols See Table...

Page 854: ...register pair HL HL register pair PC Program counter SP Stack pointer PSW Program status word CY Carry flag AC Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enabl...

Page 855: ...efix to the target instruction only one instruction immediately after the PREFIX operation code is executed as the addresses with the ES register value added A interrupt and DTC transfer are not ackno...

Page 856: ...s Clocks Flag Note 1 Note 2 Z AC CY 8 bit data transfer MOV r byte 2 1 r byte PSW byte 3 3 PSW byte CS byte 3 1 CS byte ES byte 2 1 ES byte addr16 byte 4 1 addr16 byte ES addr16 byte 5 2 ES addr16 byt...

Page 857: ...ocks Clocks Flag Note 1 Note 2 Z AC CY 8 bit data transfer MOV A sfr 2 1 A sfr sfr A 2 1 sfr A A DE 1 1 4 A DE DE A 1 1 DE A A ES DE 2 2 5 A ES DE ES DE A 2 2 ES DE A A HL 1 1 4 A HL HL A 1 1 HL A A E...

Page 858: ...oup Mnemonic Operands Bytes Clocks Clocks Flag Note 1 Note 2 Z AC CY 8 bit data transfer MOV A HL B 2 1 4 A HL B HL B A 2 1 HL B A A ES HL B 3 2 5 A ES HL B ES HL B A 3 2 ES HL B A A HL C 2 1 4 A HL C...

Page 859: ...p Mnemonic Operands Bytes Clocks Clocks Flag Note 1 Note 2 Z AC CY 8 bit data transfer XCH A HL B 2 2 A HL B A ES HL B 3 3 A ES HL B A HL C 2 2 A HL C A ES HL C 3 3 A ES HL C ONEB A 1 1 A 01H X 1 1 X...

Page 860: ...g Note 1 Note 2 Z AC CY 16 bit data transfer MOVW AX DE 1 1 4 AX DE DE AX 1 1 DE AX AX ES DE 2 2 5 AX ES DE ES DE AX 2 2 ES DE AX AX HL 1 1 4 AX HL HL AX 1 1 HL AX AX ES HL 2 2 5 AX ES HL ES HL AX 2 2...

Page 861: ...ds Bytes Clocks Clocks Flag Note 1 Note 2 Z AC CY 16 bit data transfer MOVW BC addr16 3 1 4 BC addr16 BC ES addr16 4 2 5 BC ES addr16 DE addr16 3 1 4 DE addr16 DE ES addr16 4 2 5 DE ES addr16 HL addr1...

Page 862: ...operation ADDC A byte 2 1 A CY A byte CY saddr byte 3 2 saddr CY saddr byte CY A r Note 3 2 1 A CY A r CY r A 2 1 r CY r A CY A addr16 3 1 4 A CY A addr16 CY A ES addr16 4 2 5 A CY A ES addr16 CY A sa...

Page 863: ...Note 2 Z AC CY 8 bit operation SUBC A byte 2 1 A CY A byte CY saddr byte 3 2 saddr CY saddr byte CY A r Note 3 2 1 A CY A r CY r A 2 1 r CY r A CY A addr16 3 1 4 A CY A addr16 CY A ES addr16 4 2 5 A...

Page 864: ...monic Operands Bytes Clocks Clocks Flag Note 1 Note 2 Z AC CY 8 bit operation OR A byte 2 1 A A byte saddr byte 3 2 saddr saddr byte A r Note 3 2 1 A A r r A 2 1 r r A A addr16 3 1 4 A A addr16 A ES a...

Page 865: ...maximum Table 30 14 Operation List 10 18 Instruction Group Mnemonic Operands Bytes Clocks Clocks Flag Note 1 Note 2 Z AC CY 8 bit operation CMP A byte 2 1 A byte addr16 byte 4 1 4 addr16 byte ES addr...

Page 866: ...ks Clocks Flag Note 1 Note 2 Z AC CY 16 bit operation ADDW AX word 3 1 AX CY AX word AX AX 1 1 AX CY AX AX AX BC 1 1 AX CY AX BC AX DE 1 1 AX CY AX DE AX HL 1 1 AX CY AX HL AX addr16 3 1 4 AX CY AX ad...

Page 867: ...ROM flash memory area If fetching the instruction from the internal RAM area the number becomes double number plus 3 clocks at a maximum Remark 2 MACR indicates the multiplication and accumulation reg...

Page 868: ...ddr16 ES addr16 1 saddr 2 2 saddr saddr 1 HL byte 3 2 HL byte HL byte 1 ES HL byte 4 3 ES HL byte ES HL byte 1 DEC r 1 1 r r 1 addr16 3 2 addr16 addr16 1 ES addr16 4 3 ES addr16 ES addr16 1 saddr 2 2...

Page 869: ...Am 1 Am 1 ROL A 1 2 1 CY A0 A7 Am 1 Am 1 RORC A 1 2 1 CY A0 A7 CY Am 1 Am 1 ROLC A 1 2 1 CY A7 A0 CY Am 1 Am 1 ROLWC AX 1 2 1 CY AX15 AX0 CY AXm 1 AXm 1 BC 1 2 1 CY BC15 BC0 CY BCm 1 BCm 1 Bit manipu...

Page 870: ...19 Operation List 15 18 Instruction Group Mnemonic Operands Bytes Clocks Clocks Flag Note 1 Note 2 Z AC CY Bit manipulate XOR1 CY A bit 2 1 CY CY A bit CY PSW bit 3 1 CY CY PSW bit CY saddr bit 3 1 CY...

Page 871: ...m Table 30 20 Operation List 16 18 Instruction Group Mnemonic Operands Bytes Clocks Clocks Flag Note 1 Note 2 Z AC CY Call return CALL rp 2 3 SP 2 PC 2 S SP 3 PC 2 H SP 4 PC 2 L PC CS rp SP SP 4 addr2...

Page 872: ...SP 2 rpL SP SP 2 POP PSW 2 3 PSW SP 1 SP SP 2 R R R rp 1 1 rpL SP rpH SP 1 SP SP 2 MOVW SP word 4 1 SP word SP AX 2 1 SP AX AX SP 2 1 AX SP HL SP 3 1 HL SP BC SP 3 1 BC SP DE SP 3 1 DE SP ADDW SP byt...

Page 873: ...PC 4 jdisp8 if sfr bit 0 A bit addr20 3 3 5 Note 3 PC PC 3 jdisp8 if A bit 0 PSW bit addr20 4 3 5 Note 3 PC PC 4 jdisp8 if PSW bit 0 HL bit addr20 3 3 5 Note 3 6 7 PC PC 3 jdisp8 if HL bit 0 ES HL bi...

Page 874: ...pplications TA 40 to 85 C R5F11FLxDNA Caution The RL78 microcontrollers have an on chip debug function which is provided for development and evaluation Do not use the on chip debug function in product...

Page 875: ...ter Remark 3 VSS VSSRF Reference voltage Absolute Maximum Ratings 1 2 Parameter Symbols Conditions Ratings Unit Supply voltage VDD VDD 0 5 to 3 8 Note 1 V VDDRF VCCRF VCCDDC 0 3 to 3 8 Note 1 V VSS VS...

Page 876: ...REGC 0 3 to 2 8 and 0 3 to VDD 0 3 Note V RF power supply input VREGIN REGIN 0 3 to 3 8 V RF power supply output VRFOUT1 DDCOUT 0 3 to 3 8 V VRFOUT2 VREGO1 VREGO2 VREGO3 0 3 to 1 25 V Output current...

Page 877: ...llator and XT1 oscillator refer to 6 4 System Clock Oscillator 31 2 2 On chip oscillator characteristics Note 1 High speed on chip oscillator frequency is selected with bits 0 to 4 of the option byte...

Page 878: ...the duty factor A current higher than the absolute maximum rating must not flow into one pin Note 4 100 mA for industrial applications R5F11FxxDxx Caution P02 to P04 P71 P80 to P82 and P142 to P144 do...

Page 879: ...pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin Remark Unless specified otherwise the characteristics of alternate function...

Page 880: ...to P77 P80 to P82 P100 P120 P140 to P144 Normal input buffer 0 8 VDD VDD V VIH2 P03 P04 P80 P81 P142 P143 TTL input buffer 3 3 V VDD 3 6 V 2 0 VDD V TTL input buffer 1 8 V VDD 3 3 V 1 5 VDD V VIH3 P2...

Page 881: ...Unit Output voltage high VOH1 P02 to P04 P31 P40 P70 to P72 P75 to P77 P80 to P82 P100 P120 P130 P140 to P144 2 7 V VDD 3 6 V IOH1 2 0 mA VDD 0 6 V 1 8 V VDD 3 6 V IOH1 1 5 mA VDD 0 5 V VOH2 P20 to P2...

Page 882: ...I VDD 1 A ILIH2 P20 to P22 P137 P155 P156 RESET VI VDD 1 A ILIH3 P121 to P124 X1 X2 EXCLK XT1 XT2 EXCLKS VI VDD In input port or external clock input 1 A In resonator connection 10 A Input leakage cur...

Page 883: ...rmal operation Square wave input 3 7 6 8 mA Resonator connection 3 9 7 0 fMX 8 MHz Note 2 VDD 3 0 V Normal operation Square wave input 2 0 4 1 Resonator connection 2 0 4 2 LS low speed main mode Note...

Page 884: ...ed Note 4 When high speed on chip oscillator and high speed system clock are stopped When AMPHS1 1 Ultra low power consumption oscillation However not including the current flowing into the RTC 12 bit...

Page 885: ...D 3 0 V Square wave input 0 16 0 94 Resonator connection 0 21 1 02 LS low speed main mode Note 7 fMX 8 MHz Note 3 VDD 3 0 V Square wave input 110 610 A Resonator connection 150 660 fMX 8 MHz Note 3 VD...

Page 886: ...ing ultra low current consumption AMPHS1 1 The current flowing into the RTC is included However not including the current flowing into the 12 bit interval timer and watchdog timer Note 6 Not including...

Page 887: ...icrocontrollers is the sum of IDD1 or IDD2 and IADC when the A D converter operates in an operation mode or the HALT mode Note 7 Current flowing only to the LVD circuit The supply current of the RL78...

Page 888: ...2 7 V VDD 3 6 V 0 03125 1 s 2 4 V VDD 2 7 V 0 0625 1 s LS low speed main mode 1 8 V VDD 3 6 V 0 125 1 s External system clock frequency fEX 2 7 V VDD 3 6 V 1 0 20 0 MHz 2 4 V VDD 2 7 V 1 0 16 0 MHz 1...

Page 889: ...Execution Time during Main System Clock Operation TCY vs VDD HS high speed main mode 1 0 0 1 0 10 1 0 2 0 3 0 4 0 5 0 6 0 3 6 2 7 0 01 2 4 0 03125 0 0625 0 05 Cycle time T CY s Supply voltage VDD V Du...

Page 890: ...872 of 920 Dec 22 2016 TCY vs VDD LS low speed main mode 1 0 0 1 0 10 1 0 2 0 3 0 4 0 5 0 3 6 0 01 1 8 6 0 0 125 Cycle time T CY s Supply voltage VDD V During self programming When high speed system...

Page 891: ...TIONS R01UH0575EJ0120 Rev 1 20 Page 873 of 920 Dec 22 2016 AC Timing Test Points External System Clock Timing TI TO Timing VIH VOH VIL VOL VIH VOH Test points VIL VOL EXCLK EXCLKS 1 fEX 1 fEXS tEXL tE...

Page 892: ...1H CHAPTER 31 ELECTRICAL SPECIFICATIONS R01UH0575EJ0120 Rev 1 20 Page 874 of 920 Dec 22 2016 Interrupt Request Input Timing RESET Input Timing INTP0 INTP4 INTP6 INTP7 INTP9 to INTP11 tINTL tINTH tRSL...

Page 893: ...r the TxDq pin by using port input mode register g PIMg and port output mode register g POMg UART mode connection diagram during communication at same potential 1 During communication at same potentia...

Page 894: ...n at same potential reference Remark 1 q UART number q 1 3 g PIM and POM number g 0 14 Remark 2 fMCK Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mo...

Page 895: ...20 2 During communication at same potential CSI mode master mode SCKp internal clock output TA 40 to 85 C 1 8 V VDD 3 6 V VSS 0 V Parameter Symbol Conditions HS high speed main mode LS low speed main...

Page 896: ...be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 02 11 12 CSI mode connection diagram during communication at same potential Remark p CSI number p 10 21 30 4...

Page 897: ...0 or DAPmn 1 and CKPmn 1 CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Remark 1 p CSI number p 10 21 30 Remark 2 m Unit number...

Page 898: ...ffer selected Remark 1 Vb V Communication line voltage Remark 2 q UART number q 1 3 g PIM and POM number g 0 14 Remark 3 fMCK Serial array unit operation clock frequency Operation clock to be set by t...

Page 899: ...the customer Caution and Remarks are listed on the next page 5 Communication at different potential 1 8 V 2 5 V 3 V UART mode TA 40 to 85 C 1 8 V VDD 3 6 V VSS 0 V 2 2 Parameter Symbol Conditions HS h...

Page 900: ...UART mode bit width during communication at different potential reference Remark 1 Rb Communication line TxDq pull up resistance Cb F Communication line TxDq load capacitance Vb V Communication line...

Page 901: ...SI mode master mode SCKp internal clock output TA 40 to 85 C 1 8 V VDD 3 6 V VSS 0 V 1 3 Parameter Symbol Conditions HS high speed main mode LS low speed main mode Unit MIN MAX MIN MAX SCKp cycle time...

Page 902: ...ion at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output TA 40 to 85 C 1 8 V VDD 3 6 V VSS 0 V 2 3 Parameter Symbol Conditions HS high speed main mode LS low speed ma...

Page 903: ...t different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output TA 40 to 85 C 1 8 V VDD 3 6 V VSS 0 V 3 3 Parameter Symbol Conditions HS high speed main mode LS low speed main mo...

Page 904: ...e SCKp SOp pull up resistance Cb F Communication line SCKp SOp load capacitance Vb V Communication line voltage Remark 2 p CSI number p 10 30 m Unit number m 0 1 n Channel number n 2 g PIM and POM num...

Page 905: ...iming master mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Remark 1 p CSI number p 10 30 m Unit number m 0 1 n Channel number n 2 g PIM and POM numbe...

Page 906: ...clock input TA 40 to 85 C 1 8 V VDD 3 6 V VSS 0 V Parameter Symbol Conditions HS high speed main mode LS low speed main mode Unit MIN MAX MIN MAX SCKp cycle time tKCY2 2 7 V VDD 3 6 V 2 3 V Vb 2 7 V 2...

Page 907: ...munication line voltage Remark 2 p CSI number p 10 30 m Unit number m 0 1 n Channel number n 2 g PIM and POM number g 0 14 Remark 3 fMCK Serial array unit operation clock frequency Operation clock to...

Page 908: ...iming slave mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Remark 1 p CSI number p 10 30 m Unit number m 0 1 n Channel number n 2 g PIM and POM number...

Page 909: ...in mode LS low speed main mode Unit MIN MAX MIN MAX SCLA0 clock frequency fSCL Standard mode fCLK 1 MHz 2 7 V VDD 3 6 V 0 100 0 100 kHz 1 8 V VDD 3 6 V 0 100 0 100 kHz Setup time of restart condition...

Page 910: ...peed main mode Unit MIN MAX MIN MAX SCLA0 clock frequency fSCL Fast mode fCLK 3 5 MHz 2 7 V VDD 3 6 V 0 400 0 400 kHz 1 8 V VDD 3 6 V 0 400 0 400 kHz Setup time of restart condition tSU STA 2 7 V VDD...

Page 911: ...0 to 85 C 1 8 V VDD 3 6 V VSS 0 V Parameter Symbol Conditions HS high speed main mode LS low speed main mode Unit MIN MAX MIN MAX SCLA0 clock frequency fSCL Fast mode plus fCLK 10 MHz 2 7 V VDD 3 6 V...

Page 912: ...AVREFP Reference voltage AVREFM Reference voltage VDD Reference voltage VSS ANI0 to ANI2 ANI13 ANI14 ANI19 Refer to 31 6 1 1 Refer to 31 6 1 2 1 When reference voltage AVREFP ANI0 ADREFP0 1 reference...

Page 913: ...reference voltage VSS ADREFM 0 target pin ANI0 to ANI2 ANI13 ANI14 ANI19 TA 40 to 85 C 1 8 V VDD 3 6 V VSS 0 V Reference voltage VDD Reference voltage VSS Parameter Symbol Conditions MIN TYP MAX Unit...

Page 914: ...ge 2 90 2 96 3 02 V VLVD4 Rising edge 2 86 2 92 2 97 V Falling edge 2 80 2 86 2 91 V VLVD5 Rising edge 2 76 2 81 2 87 V Falling edge 2 70 2 75 2 81 V VLVD6 Rising edge 2 66 2 71 2 76 V Falling edge 2...

Page 915: ...t voltage 2 05 2 09 2 13 V Falling interrupt voltage 2 00 2 04 2 08 V VLVDB3 LVIS1 LVIS0 0 0 Rising release reset voltage 3 07 3 13 3 19 V Falling interrupt voltage 3 00 3 06 3 12 V VLVDC0 VPOC2 VPOC1...

Page 916: ...150 200 300 kbps 4FSK GFSK 200 400 kbps Modulation index 2FSK GFSK 0 5 1 0 4FSK GFSK 0 33 Frequency band MHz Maximum frequency MHz Symbol rate ksymbol s Variable index MIN TYP MAX Unit IEEE standard...

Page 917: ...2 Compatible with ARIB Standard XIN frequency accuracy is required according to the table below to satisfy the ARIB standard Frequency band MHz Maximum frequency MHz Symbol rate ksymbols s Variable in...

Page 918: ...nput voltage VILRF STANDBY GPIO0 to GPIO4 MODE1 MODE2 0 0 1 VDDRF V High level output voltage VOHRF IOH 2 0 mA GPIO0 to GPIO4 INTOUT VDDRF 0 3 V Low level output voltage VOLRF IOL 2 0 mA GPIO0 to GPIO...

Page 919: ...m 2GFSK BT 0 5 BER 0 1 200 kbps m 1 102 97 dBm 2GFSK BT 0 5 BER 0 1 300 kbps m 0 5 97 92 dBm 4GFSK BT 0 5 BER 0 1 200 kbps m 0 33 102 97 dBm 4GFSK BT 0 5 BER 0 1 400 kbps m 0 33 100 95 dBm Maximum inp...

Page 920: ...n ratio Desired signal 3 dB above the input sensitivity level CW interferer 2 if frequency offset 25 dB TA 25 C VDDRF 3 0 V VSSRF 0 V Parameter Conditions MIN TYP MAX Unit Maximum transmission output...

Page 921: ...125 2 100 100 400 17 863 225 3 4FSK 4GFSK 200 100 0 33 5 896 MHz US 896 to 901 1 2FSK 2GFSK 10 10 0 5 25 399 896 0125 2 20 20 50 397 896 025 3 40 40 100 393 896 05 6 901 MHz US 901 to 902 1 2FSK 2GFSK...

Page 922: ...V Parameter Symbol Conditions MIN TYP MAX Unit SCKL cycle time tsccyc 250 ns SEN setup time tsesu 200 ns SEN hold time tsehd 200 ns TA 40 C to 85 C 1 8 V VDDRF 3 6 V VSSRF 0 V Parameter Symbol Conditi...

Page 923: ...eter Symbol Conditions MIN TYP MAX Unit STANDBYlow level width tstbyl 10 s OSCDRVSEL setup time From STANDBY todssu Crystal resonator 500 s DON setup time From OSCDRVSEL tdonsu Crystal resonator 50 s...

Page 924: ...RL78 G1H CHAPTER 31 ELECTRICAL SPECIFICATIONS R01UH0575EJ0120 Rev 1 20 Page 906 of 920 Dec 22 2016 Figure 31 3 Timing input external clock STANDBY tstbyl OSCDRVSEL DON RFRESETB trfrstsu2 H...

Page 925: ...reliability testing by Renesas Electronics Corporation 31 10 Dedicated Flash Memory Programmer Communication UART TA 40 to 85 C VSS 0V Parameter Symbol Conditions MIN TYP MAX Unit Data retention suppl...

Page 926: ...0 pin at the low level from when the external resets end excluding the processing time of the firmware to control the flash memory TA 40 to 85 C 1 8 V VDD 3 6 V VSS 0 V Parameter Symbol Conditions MIN...

Page 927: ...de P HVQFN64 9x9 0 50 2015 Renesas Electronics Corporation All rights reserved D E A A1 b e LP x y ZD ZE c D2 E2 8 90 8 90 0 00 0 20 0 30 Min Nom Dimensions in millimeters Reference Symbol Max 9 00 9...

Page 928: ...OUTPUT CONTROLLER p 270 Change of Figure 11 2 Format of Clock output select registers n CKSn a CHAPTER 12 WATCHDOG TIMER p 278 Addition of Note to Table 12 4 Setting Window Open Period of Watchdog Ti...

Page 929: ...ister 2 BBINTEN2 Format a p 603 Change of Figure 18 46 Receive Level Threshold Setting Register BBLVLVTH Format c p 650 Addition of descriptions to 18 4 4 89 Lower limit threshold setting register aft...

Page 930: ...uits Connection Diagram with ANTSW Addition of Figure 2 5 RL78 G1H 64 pin Peripheral Circuit Connection Diagram Using TCXO Change of Figure 4 1 Memory Map R5F11FLJ CHAPTER 4 CPU ARCHITECTURE Deletion...

Page 931: ...N2 Change of Figure 18 40 Baseband Interrupt Enable Register 2 BBINTEN2 Format Change of description in 18 4 4 35 Receive level threshold setting register BBLVLVTH Change of Figure 18 48 Count Operati...

Page 932: ...n 18 4 4 76 Short address register 1 BBSHORTAD1 Change of description in 18 4 4 77 Extended address register 1 BBEXTENDAD10 to BBEXTENDAD13 Change of description in 18 4 4 78 Receive timeout register...

Page 933: ...of 31 2 2 On chip oscillator characteristics CHAPTER 31 ELECTRICAL SPECIFICATIONS Change of 31 3 2 Supply current characteristics Addition of 31 7 2 2 Compatible with ARB Standard Change of 31 7 3 DC...

Page 934: ...Function Is Used Change of Figure 7 62 Operation Procedure When Delay Counter Function Is Used Change of remark 2 in 13 4 A D Converter Conversion Operations CHAPTER 13 TA D CONVERTER Change of remar...

Page 935: ...4 6 3 1 Baud rate calculation expression Change of remark 2 in Table 14 3 Selection of Operation Clock For UART Change of remark in 14 6 3 2 Baud rate error during transmission Change of remark in 14...

Page 936: ...Figure 18 36 Baseband Interrupt Source Register 1 BBINTREQ1 Format addition of caution Change of Figure 18 37 Baseband Interrupt Source Register 2 BBINTREQ2 Format addition of caution Change of Figur...

Page 937: ...tion of Table 18 10 Pin Status Change of Table 18 11 Description of Each State of Wake Up Operation Addition of Table 18 12 Initial setting registers Change of description in 18 6 4 2 Power Down trans...

Page 938: ...SCKp internal clock output supported only for CSI20 Change of remark 1 in 31 5 1 4 During communication at same potential CSI mode slave mode SCKp external clock input Change of remark 3 and 4 in CSI...

Page 939: ...RL78 G1H User s Manual Hardware Publication Date Rev 0 50 Sep 18 2015 Rev 1 20 Dec 22 2016 Published by Renesas Electronics Corporation...

Page 940: ...ghai P R China 200333 Tel 86 21 2226 0888 Fax 86 21 2226 0999 Renesas Electronics Hong Kong Limited Unit 1601 1611 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kon...

Page 941: ...R01UH0575EJ0120 RL78 G1H...

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