CHAPTER 15 SERIAL INTERFACE IICA
Page 459 of 920
15.5.11 Extension code
(1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag
(EXCn) is set to 1 for extension code reception and an interrupt request (INTIICAn) is issued at the falling
edge of the eighth clock. The local address stored in the slave address register n (SVAn) is not affected.
(2) The settings below are specified if 11110xx0 is transferred from the master by using a 10-bit address
transfer when the SVAn register is set to 11110xx0. Note that INTIICAn occurs at the falling edge of the
eighth clock.
• Higher four bits of data match: EXCn = 1
• Seven bits of data match:
COIn = 1
Remark
EXCn: Bit 5 of IICA status register n (IICSn)
COIn: Bit 4 of IICA status register n (IICSn)
(3) Since the processing after the interrupt request occurs differs according to the data that follows the
extension code, such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave
device, set bit 6 (LRELn) of IICA control register n0 (IICCTLn0) to 1 to set the standby mode for the next
communication operation.
Remark 1.
See the I
2
C bus specifications issued by NXP Semiconductors for details of extension codes other than those described
above.
Remark 2.
n = 0, 1
Table 15 - 3 Bit Definitions of Major Extension Codes
Slave Address
R/W Bit
Description
0000 000
0
General call address
1111 0xx
0
10-bit slave address specification (during address authentication)
1111 0xx
1
10-bit slave address specification (after address match, when read command is
issued)
Summary of Contents for RL78/G1H
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