CHAPTER 19 INTERRUPT FUNCTIONS
Page 706 of 920
Table 19 - 1 Interrupt Source List (1/2)
Note 1.
The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously.
Zero indicates the highest priority and 44 indicates the lowest priority.
Note 2.
Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 19 - 1.
Note 3.
When bit 7 (WDTINT) of the option byte (000C0H) is set to 1.
Note 4.
When bit 7 (LVIMD) of the voltage detection level register (LVIS) is cleared to 0.
Inter
rupt T
ype
Default Priority
Interrupt Source
Inter
nal/Extern
a
l
V
e
ctor T
able Address
Basi
c Configurati
on
T
ype
Name
Trigger
Maskable
0
INTWDTI
Watchdog timer interval
(75% of overflow time + 1/2 f
IL
)
Inte
rnal
0004H
(A)
1
INTLVI
Voltage detection
0006H
2
INTP0
Pin input edge detection
External
0008H
(B)
5
INTP3
Internal
000EH
6
INTP4
External
0010H
8
INTCSI20
CSI20 transfer end or buffer empty interrupt
In
ternal
0014H
(A)
9
INTCSI21
CSI21 transfer end or buffer empty interrupt
0016H
10
INTTM11H
End of timer channel 11 count or capture
(at higher 8-bit timer operation)
0018H
13
INTTM01H
End of timer channel 01 count or capture
(at higher 8-bit timer operation)
0022H
14
INTST1/
INTCSI10
UART1 transmission transfer end or buffer empty interrupt/CSI10
transfer end or buffer empty interrupt
0024H
15
INTSR1
UART1 reception transfer end
0026H
16
INTSRE1
UART1 reception communication error occurrence
0028H
INTTM03H
End of timer channel 03 count or capture
(at higher 8-bit timer operation)
17
INTIICA0
End of IICA0 communication
002AH
18
INTTM00
End of timer channel 00 count or capture
002CH
19
INTTM01
End of timer channel 01 count or capture
002EH
20
INTTM02
End of timer channel 02 count or capture
0030H
21
INTTM03
End of timer channel 03 count or capture
0032H
22
INTAD
End of A/D conversion
0034H
23
INTRTC
Fixed-cycle signal of real-time clock/alarm match detection
0036H
24
INTIT
Interval signal detection
0038H
26
INTST3/
INTCSI30
UART3 transmission transfer end or buffer empty interrupt/CSI30
transfer end or buffer empty interrupt
003CH
27
INTSR3
UART3 reception transfer end
003EH
28
INTTRJ0
Timer RJ interrupt
0040H
Summary of Contents for RL78/G1H
Page 941: ...R01UH0575EJ0120 RL78 G1H...