Chapter 5 - System Setup
5-9
PL-5910 Series User Manual
SDRAM CAS Latency Time
Designates the clock counts used, from the enabling of CAS to the start of the
burst transmission. Can be set to either [3] or [2]. Factory default setting is [3]
and strongly recommended for most users.
SDRAM Cycle Time Trans/Trc
Designates the number of SLCK's for an access cycle, i.e. the minumum re-
quired time from when a bank is activated to the activation of an identical bank.
Settings are [7/9], [5/7] or [Auto]. Factory default setting is [Auto] and strongly
recommended for most users.
SDRAM RAS-to-CAS Delay
Designates the timing delay used between RAS and CAS strobe signals. Set-
tings are [2], [3], or [Auto]. Factory default setting is [Auto] and strongly
recommended for most users.
SDRAM RAS Precharge Time
Designates the pre-charge time value used, to allow RAS to accumulate its charge
before DRAM refresh. Settings are [2], [3], or [Auto]. Factory default setting is [Auto]
and strongly recommended for most users.
Selecting the ADVANCED CHIPLET FEATURES menu item calls up the following screen.
↑↓→←
:
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
Phoenix First BIOS
(tm)
Desktop CMOS Setup Utility
Advanced ChiPLet Featrues
Item Help
Menu Level
SDRAM CAS Latency Time
[3]
SDRAM Cycle Time Tras/Trc
[Auto]
SDRAM RAS-to-CAS Delay
[Auto]
SDRAM RAS Precharge Time
[Auto]
System BIOS Cacheable
[Disabled]
Video BIOS Cacheable
[Disabled]
Memory Hole At 15M-16M
[Disabled]
CPU Latency Timer
[Enabled]
Delayed Transaction
[Enabled]
AGP Graphics Aperture Size
[65MB]
On-Chip Video Window Size
[65MB]
5.2.4 Advanced ChiPLet Features
These are ADVANCED OPTIONS. The parameters in this screen are
for system designers, service personnel, and experienced users
only. Do not reset these values unless you understand the conse-
quences of your changes.
