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8-2
Section
CPM2A/CPM2C Cycle Time and I/O Response Time
526
1, 2, 3...
1. The CPM2A/CPM2C receives an input signal just prior to the input refresh
phase of the cycle.
2. The Master’s communications servicing occurs just as the Master-to-Slave
transmission begins.
3. The Slave’s communications servicing occurs just after the transmission is
completed.
Output
point
Master’s cycle time (10 ms)
Program
execution
Transmission time (21 ms)
Slave’s cycle time (15 ms)
Min. I/O response time = 10+10+12+15+15 = 62 ms
Input
point
Input
bit
I/O refresh
Overseeing, communications
servicing, etc.
Input ON delay (10 ms)
Master to
Slave
Output ON
delay (10 ms)
Program
execution
CPU
processing
CPU
processing
Master
Slave
Maximum I/O Response Time
The CPM2A/CPM2C takes the longest to respond under the following circum-
stances:
1, 2, 3...
1. The CPM2A/CPM2C receives an input signal just after the input refresh
phase of the cycle.
2. The Master’s communications servicing just misses the Master-to-Slave
transmission.
3. The transmission is completed just after the Slave’s communications servic-
ing ends.
I/O Maximum Response Time
Input ON response time + Master’s cycle time
×
2 + Transmission time
×
3 +
Slave’s cycle time
×
2 + Output ON response time
Output
point
I/O refresh
Peripheral port servicing
Input
point
Input
bit
Program
execution
CPU
processing
Master
Slave
Input ON response time
Master #1
Trans-
mission
time
(Data transmission according to input point)
Program
execution
Program
execution
Program
execution
CPU
processing
Program
execution
Program
execution
Slave #1
Program
execution
Program
execution
Slave #2
Slave #3
Master to Slave
Trans-
mission
time
Slave to Master
Transmission time
Master to Slave
Maximum I/O response time = 10 + 10
×
2 + 12
×
3 + 15
×
2 + 15 = 111 (ms)
Output OFF
response time