8-1
Section
CPM1/CPM1A Cycle Time and I/O Response Time
513
8-1-2 CPM1/CPM1A Cycle Time
The processes involved in a single CPM1/CPM1A cycle are shown in the follow-
ing table, and their respective processing times are explained.
Process
Content
Time requirements
Overseeing
Setting cycle watchdog timer, I/O bus check, UM
check, clock refreshing, refreshing bits allocated to
new functions, etc.
0.6 ms
Program execution
User program is executed.
Total time for executing instructions.
(Varies according to content of user’s
program.)
Cycle time calculation
Standby until set time, when minimum cycle time is
set in DM 6619 of PC Setup.
Calculation of cycle time.
Almost instantaneous, except for
standby processing.
I/O refresh
Input information is read to input bits.
Output information (results of executing program) is
written to output bits.
10-point CPU :
0.06 ms
20-point CPU:
0.06 ms
30-point CPU:
0.3 ms
Expansion I/O Unit:
0.3 ms
Peripheral port servicing
Devices connected to peripheral port serviced.
0.26 ms min., 5% or less of cycle
time up to 66 ms (see note)
Note
The percentage of the cycle allocated to peripheral port servicing can be
changed in the PC Setup (DM 6617).
Cycle Time and Operations
The effects of the cycle time on CPM1/CPM1A operations are as shown below.
When a long cycle time is affecting operation, either reduce the cycle time or im-
prove responsiveness with interrupt programs.
Cycle time
Operation conditions
10 ms or longer
TIMH(15) may be inaccurate when TC 004 through TC 127 are used (operation will be normal for
TC 000 through TC 003).
20 ms or longer
Programming using the 0.02-second Clock Bit (SR 25401) may be inaccurate.
100 ms or longer
TIM may be inaccurate. Programming using the 0.1-second Clock Bit (SR 25500) may be inaccu-
rate. A CYCLE TIME OVER error is generated (SR 25309 will turn ON). See note 1.
120 ms or longer
The FALS 9F monitoring time SV is exceeded. A system error (FALS 9F) is generated, and opera-
tion stops. See note 2.
200 ms or longer
Programming using the 0.2-second Clock Bit (SR 25501) may be inaccurate.
Note
1. The PC Setup (DM 6655) can be used to disable detection of CYCLE TIME
OVER error.
2. The cycle monitoring time can be changed in the PC Setup (DM 6618).
Cycle Time Example
In this example, the cycle time is calculated for a CPM1/CPM1A CPU Unit with
20 I/O points (12 input points and 8 output points). The I/O is configured as fol-
lows:
Inputs: 1 word (00000 to 00011)
Outputs: 1 word (01000 to 01007)
The rest of the operating conditions are assumed to be as follows:
User’s program:500 instructions (consists of only LD and OUT)
Cycle time:
Variable (no minimum set)
