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8-3
Section
SRM1(-V2) Cycle Time and I/O Response Time
542
3. The transmission is completed just after the Slave’s communications servic-
ing ends.
Output
point
Master’s cycle time (10 ms)
Transmission time (39 ms
×
3)
Slave’s cycle time (15 ms)
Max. I/O response time = 8 + 10
×
2 + 39
×
3 + 15
×
2 + 10 = 185 ms
I/O refresh
Overseeing, communica-
tions, etc.
Input ON delay (8 ms)
Input
point
Input
bit
Master to
Slave
Slave to
Master
Master to
Slave
Output ON
delay (10 ms)
Program
execution
Program
execution
Program
execution
Program
execution
8-3-5 Interrupt Processing Time
This section explains the processing times involved from the time an interrupt is
executed until the interrupt processing routine is called, and from the time an in-
terrupt processing routine is completed until returning to the initial location. This
explanation applies to input, interval timer interrupts.
1, 2, 3...
1. Source of interrupt
2. Wait for completion of interrupt-mask processing
3. Change to interrupt processing
4. Interrupt routing (CPM1A only)
5. Return to initial location
The table below shows the times involved from the generation of an interrupt sig-
nal until the interrupt processing routine is called, and from when the interrupt
processing routine is completed until returning to the original position.
Item
Contents
Time
Wait for completion of
interrupt-mask processing
This is the time during which interrupts are waiting until processing has
been completed. This situation occurs when a mask processes is
executed. It is explained below in more detail.
See below.
Change to interrupt
processing
This is the time it takes to change processing to an interrupt.
15
µ
s
Return
This is the time it takes, from execution of RET(93), to return to the proces-
sing that was interrupted.
15
µ
s
Mask Processing
Interrupts are masked during processing of the operations described below. Un-
til the processing is completed, any interrupts will remain masked for the indi-
cated times.
Generation and clearing of non-fatal errors:
When a non-fatal error is generated and the error contents are registered at
the SRM1(-V2), or when an error is being cleared, interrupts will be masked
for a maximum of 100
µ
s until the processing has been completed.