NXP Semiconductors LPC84x, User Manual

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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 88 of 515
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Chapter 8: LPC84x System configuration (SYSCON)
CLKOUTSEL R/W 0x0F0 CLKOUT clock source select 0 8.6.32
CLKOUTDIV R/W 0x0F4 CLKOUT clock divider 0 8.6.33
- - 0x0F8 Reserved - -
EXTTRACECMD R/W 0x0FC External trace buffer command register 0 8.6.34
PIOPORCAP0 R 0x100 POR captured PIO0 status 0 user
dependent 8.6.35
PIOPORCAP1 R 0x104 POR captured PIO1 status 0 user
dependent 8.6.36
- - 0x108 -
0x130 Reserved - -
IOCONCLKDIV6 R/W 0x134 Peripheral clock 6 to the IOCON block for
programmable glitch filter 0 8.6.37
IOCONCLKDIV5 R/W 0x138 Peripheral clock 5 to the IOCON block for
programmable glitch filter 0 8.6.37
IOCONCLKDIV4 R/W 0x13C Peripheral clock 4 to the IOCON block for
programmable glitch filter 0 8.6.37
IOCONCLKDIV3 R/W 0x140 Peripheral clock 3 to the IOCON block for
programmable glitch filter 0 8.6.37
IOCONCLKDIV2 R/W 0x144 Peripheral clock 2 to the IOCON block for
programmable glitch filter 0 8.6.37
IOCONCLKDIV1 R/W 0x148 Peripheral clock 1 to the IOCON block for
programmable glitch filter 0 8.6.37
IOCONCLKDIV0 R/W 0x14C Peripheral clock 0 to the IOCON block for
programmable glitch filter 0 8.6.37
BODCTRL R/W 0x150 Brown-Out Detect 0 8.6.38
SYSTCKCAL R/W 0x154 System tick counter calibration 0 8.6.39
- R/W 0x158 -
0x16C Reserved - -
IRQLATENCY R/W 0x170 IRQ delay. Allows trade-off between interrupt
latency and determinism. 0x0000 0010 8.6.40
NMISRC R/W 0x174 NMI Source Control 0 8.6.41
PINTSEL0 R/W 0x178 GPIO Pin Interrupt Select register 0 0 8.6.42
PINTSEL1 R/W 0x17C GPIO Pin Interrupt Select register 1 0 8.6.42
PINTSEL2 R/W 0x180 GPIO Pin Interrupt Select register 2 0 8.6.42
PINTSEL3 R/W 0x184 GPIO Pin Interrupt Select register 3 0 8.6.42
PINTSEL4 R/W 0x188 GPIO Pin Interrupt Select register 4 0 8.6.42
PINTSEL5 R/W 0x18C GPIO Pin Interrupt Select register 5 0 8.6.42
PINTSEL6 R/W 0x190 GPIO Pin Interrupt Select register 6 0 8.6.42
PINTSEL7 R/W 0x194 GPIO Pin Interrupt Select register 7 0 8.6.42
- - 0x198 -
0x200 Reserved - -
STARTERP0 R/W 0x204 Start logic 0 pin wake-up enable register 0 8.6.43
- - 0x208 -
0x210 Reserved - -
STARTERP1 R/W 0x214 Start logic 1 interrupt wake-up enable register 0 8.6.44
Table 125. Register overview: System configuration (base address 0x4004 8000)
…continued
Name Access Offset Description Reset value Section