UM11029
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User manual
Rev. 1.0 — 16 June 2017
107 of 515
NXP Semiconductors
UM11029
Chapter 8: LPC84x System configuration (SYSCON)
8.6.30 Fractional generator 1 multiplier value register
The UART, I
2
C, and SPI clocks come from the FCLK multiplexer. The FRG1CLK is one
clock source of the FCLK multiplexer and its output from the fractional generator 1 can be
adjusted by a fractional divider:
frg1clk = frg1_src_clk/(1 + MULT/DIV).
FRG1_SRC_CLK is input clock of fractional generator 1, which can be the FRO, main
clock, or sys pll clock.
The fractional portion (1 + MULT/DIV) is determined by the two fractional divider registers
in the SYSCON block:
•
The DIV denominator of the fractional divider value is programmed in the FRG1DIV
register. See
.
•
The MULT value programmed in this register is the numerator of the fractional divider
value used by the fractional rate generator to create the fractional component to the
baud rate.
See also:
Section 17.3.1 “Configure the USART clock and baud rate”
.
Section 17.7.1 “Clocking and baud rates”
.
8.6.31 FRG1 clock source select register
The FRG1CLKSEL register selects the frg1_src clock, which can be the FRO, main clock,
or sys_pll.
Table 154. Fractional generator 1 divider value register (FRG1DIV, address 0x4004 80E0) bit description
Bit
Symbol
Value
Description
Reset
value
7:0
DIV
Denominator of the fractional divider. DIV is equal to the programmed value
+1. Always set to 0xFF to use with the fractional baud rate generator.
0
31:8
-
Reserved
-
Table 155. Fractional generator 1 multiplier value register (FRG1MULT, address 0x4004
80E4) bit description
Bit
Symbol
Value
Description
Reset
value
7:0
MULT
Numerator of the fractional divider. MULT is equal to the
programmed value.
0
31:8
-
Reserved
-