UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
251 of 515
NXP Semiconductors
UM11029
Chapter 15: LPC84x Reduced power modes and power management
1
WAKEPAD_
DISABLE
WAKEUP pin disable. Setting this bit disables the wake-up pin, so it can be
used for other purposes.
Remark:
Setting this bit is not necessary if deep power-down mode is not
used.
0
0
Enabled. The wake-up function is enabled on pin PIO0_4.
1
Disabled. Setting this bit disables the wake-up function on pin PIO0_4.
2
LPOSCEN
Enable the low-power oscillator for use with the 10 kHz self-wake-up timer
clock. You must set this bit if the CLKSEL bit in the self-wake-up timer CTRL
bit is set.
Do not enable the low-power oscillator if the self-wake-up timer is clocked by
the divided FRO or the external clock input.
0
0
Disabled.
1
Enabled.
3
LPOSCDPDEN
Enable the low-power oscillator in deep power-down mode. Setting this bit
causes the low-power oscillator to remain running during deep power-down
mode provided that bit 2 in this register is set as well.
You must set this bit for the self-wake-up timer to be able to wake up the part
from deep power-down mode.
Remark:
Do not set this bit unless you use the self-wake-up timer with the
low-power oscillator clock source to wake up from deep power-down mode.
0
0
Disabled.
1
Enabled.
4
WAKEUPCLKHYS
External clock input for the self-wake-up timer WKTCLKIN hysteresis enable.
0
0
Disabled. Hysteresis for WAKEUP clock pin disabled.
1
Enabled. Hysteresis for WAKEUP clock pin enabled.
5
WAKECLKPAD_
DISABLE
Disable the external clock input for the self-wake-up timer. Setting this bit
enables the self-wake-up timer clock pin WKTCLKLIN. To minimize power
consumption, especially in deep power-down mode, disable this clock input
when not using the external clock option for the self-wake-up timer.
0
0
Disabled. Setting this bit disables external clock input on pin PIO0_28.
1
Enabled. The external clock input for the self-wake-up timer is enabled on pin
PIO0_28.
6
RESETHYS
RESET pin hysteresis enable.
0
0
Disabled. Hysteresis for RESET pin disabled.
1
Enabled. Hysteresis for RESET pin enabled.
7
RESET_
DISABLE
RESET pin disable. Setting this bit disables the reset wake-up function, so the
pin can be used for other purposes.
Remark:
Setting this bit is not necessary if deep power-down mode is not
used.
0
0
Enabled. The reset wake-up function is enabled on pin PIO0_5.
1
Disabled. Setting this bit disables the wake-up function on pin PIO0_5.
31:8
-
Data retained during deep power-down mode.
0x0
Table 293. Deep power down control register (DPDCTRL, address 0x4002 0014) bit description
…continued
Bit
Symbol
Value
Description
Reset
value
