UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
460 of 515
NXP Semiconductors
UM11029
Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC)
•
Disabled: Threshold comparisons on channel n will not generate an A/D
threshold-compare interrupt request.
•
Outside threshold: A conversion result on channel n which is outside the range
specified by the designated HIGH and LOW threshold registers will set the channel n
THCMP flag in the FLAGS register and generate an A/D threshold-compare interrupt
request.
•
Crossing threshold: Detection of a threshold crossing on channel n will set the
channel n THCMP flag in the ADFLAGS register and generate an A/D
threshold-compare interrupt request.
Remark:
Overrun and threshold-compare interrupts related to a particular channel will
occur regardless of which sequence was in progress at the time the conversion was
performed or what trigger caused the conversion.
Table 454. A/D Interrupt Enable register (INTEN, address 0x4001 C064 ) bit description
Bit
Symbol
Value
Description
Reset
value
0
SEQA_INTEN
Sequence A interrupt enable.
0
0
Disabled. The sequence A interrupt/DMA trigger is disabled.
1
Enabled. The sequence A interrupt/DMA trigger is enabled and will be
asserted either upon completion of each individual conversion performed as
part of sequence A, or upon completion of the entire A sequence of
conversions, depending on the MODE bit in the SEQA_CTRL register.
1
SEQB_INTEN
Sequence B interrupt enable.
0
0
Disabled. The sequence B interrupt/DMA trigger is disabled.
1
Enabled. The sequence B interrupt/DMA trigger is enabled and will be
asserted either upon completion of each individual conversion performed as
part of sequence B, or upon completion of the entire B sequence of
conversions, depending on the MODE bit in the SEQB_CTRL register.
2
OVR_INTEN
Overrun interrupt enable.
0
0
Disabled. The overrun interrupt is disabled.
1
Enabled. The overrun interrupt is enabled. Detection of an overrun condition
on any of the 12 channel data registers will cause an overrun interrupt
request.
In addition, if the MODE bit for a particular sequence is 0, then an overrun in
the global data register for that sequence will also cause this interrupt request
to be asserted.
4:3
ADCMPINTEN0
Threshold comparison interrupt enable.
00
0x0
Disabled.
0x1
Outside threshold.
0x2
Crossing threshold.
0x3
Reserved
6:5
ADCMPINTEN1
Threshold comparison interrupt enable.
00
0x0
Disabled.
0x1
Outside threshold.
0x2
Crossing threshold.
0x3
Reserved.