UM11029
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User manual
Rev. 1.0 — 16 June 2017
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NXP Semiconductors
UM11029
Chapter 21: LPC84x SCTimer/PWM
21.6.1.5 Event select registers for setting or clearing the outputs
This group contains the registers that select the events which affect the level of each
SCTimer/PWM output. Also included are registers to manage conflicts that occur when
events try to set or clear the same output. This register group includes the following
registers:
•
One OUTn_SET register for each output to select the events which set the output.
•
One OUTn_CLR register for each output to select the events which clear the output.
•
The conflict resolution register which defines an action when more than one event try
to control an output at the same time.
•
The conflict flag and conflict interrupt enable registers that monitor interrupts arising
from output set and clear conflicts.
•
The output direction control register that interchanges the set and clear output
operation caused by an event in bidirectional mode.
The OUTn_SET and OUTn_CLR registers each contain one bit per event that selects
whether the event changes the state a given output n.
In the dual-counter mode, the events can be selected independently for each output.
21.6.1.6 Event select registers for capturing a counter value
This group contains registers that select events which capture the counter value and store
it in one of the CAP registers. Each capture register m has one associated CAPCTRLm
register which in turn selects the events to capture the counter value.
21.6.1.7 Event select register for initiating DMA transfers
One register is provided for each of the two DMA requests to select the events that can
trigger a DMA request.
The DMAREQn register contain one bit for each event that selects whether this event
triggers a DMA request. An additional bit enables the DMA trigger when the match
registers are reloaded.
21.6.1.8 Interrupt handling registers
The following registers provide flags that are set by events and select the events that
when they occur request an interrupt.
•
The event flag register provides one flag for each event that is set when the event
occurs.
•
The event flag interrupt enable register provides one bit for each event to be enabled
for the SCTimer/PWM interrupt.
21.6.1.9 Registers for controlling SCTimer/PWM inputs and outputs by software
Two registers are provided that allow software (as opposed to events) to set input and
outputs of the SCTimer/PWM:
•
The SCTimer/PWM input register to read the state of any of the SCTimer/PWM inputs.
•
The SCTimer/PWM output register to set or clear any of the SCTimer/PWM outputs or
to read the state of the outputs.
