UM11029
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User manual
Rev. 1.0 — 16 June 2017
397 of 515
NXP Semiconductors
UM11029
Chapter 21: LPC84x SCTimer/PWM
21.6.16 SCTimer/PWM event interrupt enable register
This register enables flags to request an interrupt if the FLAGn bit in the SCTimer/PWM
event flag register (
) is also set.
21.6.17 SCTimer/PWM event flag register
This register records events. Writing ones to this register clears the corresponding flags
and negates the SCTimer/PWM interrupt request if all enabled flag register bits are zero.
Table 399. SCTimer/PWM DMA 0 request register (DMAREQ0, offset 0x05C) bit description
Bit
Symbol
Description
Reset
value
5:0
DEV_0
If bit n is one, event n triggers DMA request 0 (event 0 = bit 0,
event 1 = bit 1,..., event 7 = bit 7).
0
29:6
-
Reserved
-
30
DRL0
A 1 in this bit triggers DMA request 0 when it loads the
Match_L/Unified registers from the Reload_L/Unified registers.
0
31
DRQ0
This read-only bit indicates the state of DMA Request 0.
Note that if the related DMA channel is enabled and properly set
up, it is unlikely that software will see this flag, it will be cleared
rapidly by the DMA service. The flag remaining set could point
to an issue with DMA setup.
0
Table 400. SCTimer/PWM DMA 1 request register (DMAREQ1, offset 0x060) bit description
Bit
Symbol
Description
Reset
value
5:0
DEV_1
If bit n is one, event n triggers DMA request 1 (event 0 = bit 0,
event 1 = bit 1,..., event 7 = bit 7).
0
29:6
-
Reserved
-
30
DRL1
A 1 in this bit triggers DMA request 1 when it loads the Match
L/Unified registers from the Reload L/Unified registers.
0
31
DRQ1
This read-only bit indicates the state of DMA Request 1.
Note that if the related DMA channel is enabled and properly set
up, it is unlikely that software will see this flag, it will be cleared
rapidly by the DMA service. The flag remaining set could point
to an issue with DMA setup.
0
Table 401. SCTimer/PWM event interrupt enable register (EVEN, offset 0x0F0) bit description
Bit
Symbol
Description
Reset
value
7:0
IEN
The SCTimer/PWM requests an interrupt when bit n of this register
and the event flag register are both one (event 0 = bit 0, event 1 =
bit 1,..., event 7 = bit 7).
0
31:8
-
Reserved
-