UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
326 of 515
NXP Semiconductors
UM11029
Chapter 18: LPC84x SPI0/1
18.7.3 Clocking and data rates
In order to use the SPI, clocking details must be defined. This includes configuring the
system clock and selection of the clock divider value in DIV. See
.
18.7.3.1 Data rate calculations
The SPI interface is designed to operate asynchronously from any on-chip clocks, and
without the need for overclocking.
In slave mode, this means that the SCK from the external master is used directly to run
the transmit and receive shift registers and other logic.
In master mode, the SPI rate clock produced by the SPI clock divider is used directly as
the outgoing SCK.
The SPI clock divider is an integer divider. The SPI in master mode can be set to run at
the same speed as the selected PCLK, or at lower integer divide rates. The SPI rate will
be = PCLK_SPIn / DIVVAL.
In slave mode, the clock is taken from the SCK input and the SPI clock divider is not used.
18.7.4 Slave select
The SPI block provides for four Slave Select inputs in slave mode or outputs in master
mode. Each SSEL can be set for normal polarity (active low), or can be inverted (active
high). Representation of the 4 SSELs in a register is always active low. If an SSEL is
inverted, this is done as the signal leaves/enters the SPI block.
In slave mode,
any
asserted SSEL that is connected to a pin will activate the SPI. In
master mode, all SSELs that are connected to a pin will be output as defined in the SPI
registers. In the latter case, the SSELs could potentially be decoded externally in order to
address more than four slave devices. Note that at least one SSEL is asserted when data
is transferred in master mode.
In master mode, Slave Selects come from the SSELN field, which appears in both the
CTL and DATCTL registers. In slave mode, the state of all four SSELs is saved along with
received data in the RXSSEL_N field of the RXDAT register.