UM11029
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User manual
Rev. 1.0 — 16 June 2017
254 of 515
NXP Semiconductors
UM11029
Chapter 15: LPC84x Reduced power modes and power management
15.7.3.1 Power configuration in Active mode
Power consumption in Active mode is determined by the following configuration choices:
•
The SYSAHBCLKCTRL register controls which memories and peripherals are
running (
•
The power to various analog blocks (PLL, oscillators, the BOD circuit, the ADC block,
the comparator block, the FAIM block, and the flash block) can be controlled at any
time individually through the PDRUNCFG register (
Table 172 “Power configuration
register (PDRUNCFG, address 0x4004 8238) bit description”
).
•
The clock source for the system clock can be selected from the
FRO
(default), the
system oscillator, external clock, the watchdog oscillator, or the divided FRO (see
and related registers).
•
The system clock frequency can be selected by the SYSPLLCTRL (
) and
the SYSAHBCLKDIV register (
).
•
The USART, ADC, SCTimer/PWM, and CLKOUT use individual peripheral clocks with
their own clock dividers. The peripheral clocks can be shut down through the
corresponding clock divider registers.
15.7.4 Sleep mode
In sleep mode, the system clock to the ARM Cortex-M0+ core is stopped and execution of
instructions is suspended until either a reset or an interrupt occurs.
Peripheral functions, if selected to be clocked in the SYSAHBCLKCTRL register, continue
operation during sleep mode and may generate interrupts to cause the processor to
resume execution. Sleep mode eliminates dynamic power used by the processor itself,
memory systems and related controllers, and internal buses. The processor state and
registers, peripheral registers, and internal SRAM values are maintained, and the logic
levels of the pins remain static.
15.7.4.1 Power configuration in sleep mode
Power consumption in sleep mode is configured by the same settings as in Active mode:
•
The clock remains running.
•
The system clock frequency remains the same as in Active mode, but the processor is
not clocked.
•
Analog and digital peripherals are selected as in Active mode.
15.7.4.2 Programming sleep mode
The following steps must be performed to enter sleep mode:
1. The PM bits in the PCON register must be set to the default value 0x0.
2. The SLEEPDEEP bit in the ARM Cortex-M0+ SCR register must be set to zero
(
3. Use the ARM Cortex-M0+ Wait-For-Interrupt (WFI) instruction.
