NXP Semiconductors LPC84x, User Manual

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User manual Rev. 1.0 — 16 June 2017 235 of 515
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Chapter 13: LPC84x Pin interrupts/pattern match engine
13.7 Functional description
13.7.1 Pin interrupts
In this interrupt facility, up to 8 pins are identified as interrupt sources by the Pin Interrupt
Select registers (PINTSEL0-7). All registers in the pin interrupt block contain 8 bits,
corresponding to the pins called out by the PINTSEL0-7 registers. The ISEL register
defines whether each interrupt pin is edge- or level-sensitive. The RISE and FALL
registers detect edges on each interrupt pin, and can be written to clear (and set) edge
detection. The IST register indicates whether each interrupt pin is currently requesting an
interrupt, and this register can also be written to clear interrupts.
The other pin interrupt registers play different roles for edge-sensitive and level-sensitive
pins, as described in
Table 282 .
31:29 CFG7 Specifies the match contribution condition for bit slice 7. 0b000
0x0 Constant HIGH. This bit slice always contributes to a product term match.
0x1 Sticky rising edge. Match occurs if a rising edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x2 Sticky falling edge. Match occurs if a falling edge on the specified input has occurred
since the last time the edge detection for this bit slice was cleared. This bit is only
cleared when the PMCFG or the PMSRC registers are written to.
0x3 Sticky rising or falling edge. Match occurs if either a rising or falling edge on the
specified input has occurred since the last time the edge detection for this bit slice
was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are
written to.
0x4 High level. Match (for this bit slice) occurs when there is a high level on the input
specified for this bit slice in the PMSRC register.
0x5 Low level. Match occurs when there is a low level on the specified input.
0x6 Constant 0. This bit slice never contributes to a match (should be used to disable any
unused bit slices).
0x7 Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a
rising or falling edge is first detected on the specified input (this is a non-sticky
version of value 0x3). This bit is cleared after one clock cycle.
Table 281. Pattern match bit slice configuration register (PMCFG, address 0xA000 4030) bit description
…continued
Bit Symbol Value Description Reset
value
Table 282. Pin interrupt registers for edge- and level-sensitive pins
Name Edge-sensitive function Level-sensitive function
IENR Enables rising-edge interrupts. Enables level interrupts.
SIENR Write to enable rising-edge interrupts. Write to enable level interrupts.
CIENR Write to disable rising-edge interrupts. Write to disable level interrupts.
IENF Enables falling-edge interrupts. Selects active level.
SIENF Write to enable falling-edge interrupts. Write to select high-active.
CIENF Write to disable falling-edge interrupts. Write to select low-active.