UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
439 of 515
NXP Semiconductors
UM11029
Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC)
•
Calibration is required after every power-up or wake-up from Deep power-down
mode. See
Section 26.3.4 “Hardware self-calibration”
.
•
For a sampling rate higher than 1 Msamples/s, VDDA must be higher than 2.7 V. See
•
Configure the ADC for the appropriate analog supply voltage using the TRM register
(
). The default setting assumes V
DDA
2.7 V.
26.3.1 Perform a single ADC conversion using a software trigger
Remark:
When A/D conversions are triggered by software only and hardware triggers are
not used in the conversion sequence, set the trigger source in the SEQA_CTRL and
SEQB_CTRL registers to 0x0 (default).
Once the sequence is enabled, the ADC converts a sample whenever the START bit is
written to. The TRIGPOL bit can be set in the same write that sets the SEQ_ENA and the
START bits. Be careful not to modify the TRIGGER, TRIGPOL, and SEQ_ENA bits on
subsequent writes to the START bit. See also
Section 26.7.2.1 “Avoiding spurious
.
The ADC converts an analog input signal VIN on the ADC_[11:0]. The VREFP and
VREFN pins provide a positive and negative reference voltage input. The result of the
conversion is (4095 x VIN- VREFN)/(VREFP - VREFN). The result of an input voltage
below VREFN is 0, and the result of an input voltage above VREFP is 4095 (0xFFF).
To perform a single ADC conversion for ADC channel 1 using the analog signal on pin
ADC_1, follow these steps:
1. Enable the analog function ADC_1.
2. Configure the system clock to be 25 MHz and select a CLKDIV value of 0 for a
sampling rate of 1 Msamples/s using the ADC CTRL register.
3. Select ADC channel 1 to perform the conversion by setting the CHANNELS bits to
0x2 in the SEQA_CTL register.
4. Set the TRIGPOL bit to 1 and the SEQA_ENA bit to 1 in the SEQA_CTRL register.
5. Set the START bit to 1 in the SEQA_CTRL register.
6. Read the RESULT bits in the DAT1 register for the conversion result.
Fig 60. ADC clocking
CTRL register
Clock generation
ADC
SYSCON
ANALOG-to-
DIGITAL
CONVERSION
CLKDIV
system clock
SYSAHBCLKCTRL[24]
