UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
446 of 515
NXP Semiconductors
UM11029
Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC)
26.6.2 A/D Conversion Sequence A Control Register
There are two, independent conversion sequences that can be configured, each
consisting of a set of conversions on one or more channels. This control register specifies
the channel selection and trigger conditions for the A sequence and contains bits to allow
software to initiate that conversion sequence.
To avoid conversions on spurious triggers, only change the trigger configuration when the
conversion sequence is disabled. A conversion can be triggered by software or hardware
in the conversion sequence, but if conversions are triggered by software only, spurious
hardware triggers must be prevented. See
Section 26.3.1 “Perform a single ADC
conversion using a software trigger”
.
Remark:
Set the BURST and SEQU_ENA bits at the same time.
Table 443. A/D Control Register (CTRL, addresses 0x4001 C000) bit description
Bit
Symbol
Value
Description
Reset
value
7:0
CLKDIV
The system clock is divided by this value plus one to produce the sampling clock.
The sampling clock should be less than or equal to 30 MHz for 1.2 Msamples/s.
Typically, software should program the smallest value in this field that yields this
maximum clock rate or slightly less, but in certain cases (such as a
high-impedance analog source) a slower clock may be desirable.
0
9:8
-
Reserved. Do not write a one to these bits.
0
10
LPWRMODE
Select low-power ADC mode.
The analog circuitry is automatically powered-down when no conversions are
taking place. When any (hardware or software) triggering event is detected, the
analog circuitry is enabled. After the required start-up time, the requested
conversion will be launched. Once the conversion completes, the analog-circuitry
will again be powered-down provided no further conversions are pending.
Using this mode can save an appreciable amount of current when conversions are
required relatively infrequently.
The penalty for using this mode is an approximately 15 ADC clock delay, based on
the frequency specified in the CLKDIV field, from the time the trigger event occurs
until sampling of the A/D input commences.
Remark:
This mode will NOT power-up the ADC when the ADC analog block is
powered down in the system control block.
0
0
Disabled. The low-power ADC mode is disabled.
The analog circuitry remains activated even when no conversions are requested.
1
Enabled. The low-power ADC mode is enabled.
29:11
Reserved, do not write ones to reserved bits.
0
30
CALMODE
Writing a 1 to this bit initiates a self-calibration cycle. This bit will be automatically
cleared by hardware after the calibration cycle is complete. To calibrate the ADC,
set the ADC clock to 500 kHz.
Remark:
Other bits of this register may be written to concurrently with setting this
bit, however once this bit has been set no further writes to this register are
permitted until the full calibration cycle has ended.
0
31
-
Reserved.
0
