UM11029
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
104 of 515
NXP Semiconductors
UM11029
Chapter 8: LPC84x System configuration (SYSCON)
8.6.25 Peripheral clock source select registers
The peripheral clock source select registers select function clock sources for the serial
peripherals shown in the following list. The potential clock sources are the same for each
peripheral. See
•
UART0 clock source select register (UART0CLKSEL, address 0x4004 8090.
•
UART1 clock source select register (UART1CLKSEL, address 0x4004 8094).
•
UART2 clock source select register (UART2CLKSEL, address 0x4004 8098).
•
UART3 clock source select register (UART3CLKSEL, address 0x4004 809C).
•
UART4 clock source select register (UART4CLKSEL, address 0x4004 80A0).
•
I
2
C0 clock source select register (I2C0CLKSEL, address 0x4004 80A4).
•
I
2
C1 clock source select register (I
2
C1CLKSEL, address 0x4004 80A8).
•
I
2
C2 clock source select register (I
2
C2CLKSEL, address 0x4004 80AC).
•
I
2
C3 clock source select register (I
2
C3CLKSEL, address 0x4004 80AC).
•
SPI0 clock source select register (SPI0CLKSEL, address 0x4004 80B4).
•
SPI1 clock source select register (SPI1CLKSEL, address 0x4004 80B8).
8.6.26 Fractional generator 0 divider value register
The UART, I
2
C, SPI clock come from the FCLK multiplexer. The FRGCLK0 is one clock
source of the FCLK multiplexer and its output from the fractional generator 0 can be
adjusted by a fractional divider:
frg0clk = frg0_src_clk/(1 + MULT/DIV).
FRG0_SRC_CLK is input clock of fractional generator 0, which can be the FRO, main
clock, or sys pll clock.
The fractional portion (1 + MULT/DIV) is determined by the two fractional divider registers
in the SYSCON block:
•
The DIV value programmed in this register is the denominator of the divider used by
the fractional rate generator to create the fractional component of FRG0CLK.
Table 150. Peripheral clock source select registers
Bit
Symbol
Value
Description
Reset
value
2:0
SEL
Peripheral clock source
0x7
0x0
FRO
0x1
Main clock
0x2
FRG0 clock
0x3
FRG1 clock
0x4
FRO_DIV = FRO / 2
0x5
Reserved
0x6
Reserved
0x7
None
31:3
-
-
Reserved
-
