UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
312 of 515
NXP Semiconductors
UM11029
Chapter 18: LPC84x SPI0/1
18.6.2 SPI Delay register
The DLY register controls several programmable delays related to SPI signalling. These
delays apply only to master mode, and are all stated in SPI clocks.
Timing details are shown in:
Section 18.7.2.1 “Pre_delay and Post_delay”
Section 18.7.2.2 “Frame_delay”
4
CPHA
Clock Phase select.
0
0
Change. The SPI captures serial data on the first clock transition of the transfer (when
the clock changes away from the rest state). Data is changed on the following edge.
1
Capture. The SPI changes serial data on the first clock transition of the transfer (when
the clock changes away from the rest state). Data is captured on the following edge.
5
CPOL
Clock Polarity select.
0
0
Low. The rest state of the clock (between transfers) is low.
1
High. The rest state of the clock (between transfers) is high.
6
-
Reserved. Read value is undefined, only zero should be written.
NA
7
LOOP
Loopback mode enable. Loopback mode applies only to Master mode, and connects
transmit and receive data connected together to allow simple software testing.
0
0
Disabled.
1
Enabled.
8
SPOL0
SSEL0 Polarity select.
0
0
Low. The SSEL0 pin is active low. The value in the SSEL0 fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL0 is not inverted relative to the pins.
1
High. The SSEL0 pin is active high. The value in the SSEL0 fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL0 is inverted relative to the pins.
9
SPOL1
SSEL1 Polarity select.
0
0
Low. The SSEL1 pin is active low. The value in the SSEL1 fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL1 is not inverted relative to the pins.
1
High. The SSEL1 pin is active high. The value in the SSEL1 fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL1 is inverted relative to the pins.
10
SPOL2
SSEL2 Polarity select.
0
0
Low. The SSEL2 pin is active low. The value in the SSEL2 fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL2 is not inverted relative to the pins.
1
High. The SSEL2 pin is active high. The value in the SSEL2 fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL2 is inverted relative to the pins.
11
SPOL3
SSEL3 Polarity select.
0
0
Low. The SSEL3 pin is active low. The value in the SSEL3 fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL3 is not inverted relative to the pins.
1
High. The SSEL3 pin is active high. The value in the SSEL3 fields of the RXDAT,
TXDATCTL, and TXCTL registers related to SSEL3 is inverted relative to the pins.
31:12 -
Reserved. Read value is undefined, only zero should be written.
NA
Table 337. SPI Configuration register (CFG, addresses 0x4005 8000 (SPI0), 0x4005 C000 (SPI1)) bit
description
…continued
Bit
Symbol
Value Description
Reset
value
