NXP Semiconductors LPC84x, User Manual

Page: 82 / 515

UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 82 of 515
NXP Semiconductors
UM11029
Chapter 8: LPC84x System configuration (SYSCON)
8.4 Pin description
The SYSCON inputs and outputs are assigned to external pins through the switch matrix.
See Section 10.3.1 “Connect an internal signal to a package pin” to assign the CLKOUT
function to a pin.
See Section 10.3.2 to enable the clock input, the oscillator pins, and the external reset
input.
8.5 General description
8.5.1 Clock generation
The system control block generates all clocks for the chip. Only the low-power oscillator
used for wake-up timing is controlled by the PMU. Except for the USART clock, SPI clock,
I
2
C clock, SCTimer/PWM clock, ADC clock, and the clock to configure the glitch filters of
the digital I/O pins, the clocks to the core and peripherals run at the same frequency. The
maximum system clock frequency is 30 MHz. See
Figure 7 .
Remark:
The main clock frequency is limited to 100 MHz.
Table 123. SYSCON pin description
Function Direction Pin Description SWM register Reference
CLKOUT O any CLKOUT clock output. PINASSIGN8 Table 188
CLKIN I PIO0_1/ACMP_I1/CLKIN External clock input to the system
PLL. Disable the ACMP_I1 function
in the PINENABLE register. PINENABLE0 Table 195
XTALIN I PIO0_8/XTALIN Input to the system oscillator. PINENABLE0 Table 195
XTALOUT O PIO0_9/XTALOUT Output from the system oscillator. PINENABLE0 Table 195
RESET I RESET/PIO0_5 External reset input PINENABLE0 Table 195