UM11029
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
181 of 515
NXP Semiconductors
UM11029
Chapter 11: LPC84x I/O configuration (IOCON)
11.5.31 PIO1_9 register
15:13 CLK_DIV
Select peripheral clock divider for input filter sampling clock.
Value 0x7 is reserved.
0
0x0
IOCONCLKDIV0.
0x1
IOCONCLKDIV1.
0x2
IOCONCLKDIV2.
0x3
IOCONCLKDIV3.
0x4
IOCONCLKDIV4.
0x5
IOCONCLKDIV5.
0x6
IOCONCLKDIV6.
31:16 -
-
Reserved.
0
Table 228. PIO1_8 register (PIO1_8, address 0x4004 407C) bit description
Bit
Symbol
Value
Description
Reset value
Table 229. PIO1_9 register (PIO1_9, address 0x4004 4080) bit description
Bit
Symbol
Value
Description
Reset value
2:0
-
Reserved.
0
4:3
MODE
Selects function mode (on-chip pull-up/pull-down resistor
control).
FAIM value dependent
0x0
Inactive (no pull-down/pull-up resistor enabled).
0x1
Pull-down resistor enabled.
0x2
Pull-up resistor enabled.
0x3
Repeater mode.
5
HYS
Hysteresis.
1
0
Disable.
1
Enable.
6
INV
Invert input
0
0
Input not inverted (HIGH on pin reads as 1; LOW on pin reads
as 0).
1
Input inverted (HIGH on pin reads as 0, LOW on pin reads as
1).
9:7
-
-
Reserved.
0b001
10
OD
Open-drain mode.
0
0
Disable.
1
Open-drain mode enabled.
Remark:
This is not a true open-drain mode.
12:11
S_MODE
Digital filter sample mode.
0
0x0
Bypass input filter.
0x1
1 clock cycle. Input pulses shorter than one filter clock are
rejected.
0x2
2 clock cycles. Input pulses shorter than two filter clocks are
rejected.
0x3
3 clock cycles. Input pulses shorter than three filter clocks are
rejected.