NXP Semiconductors LPC84x, User Manual

Page: 259 / 515

UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 259 of 515
NXP Semiconductors
UM11029
Chapter 15: LPC84x Reduced power modes and power management
1. Enable the low-power oscillator to run in deep power-down mode by setting bits 2 and
3 in the DPDCTRL register to 1 (see Table 293 )
2. Ensure that bit 3 in the PCON register ( Table 291 ) is cleared.
3. Write 0x3 to the PM bits in the PCON register (see Table 291 ).
4. Store data to be retained in the general purpose registers ( Section 15.6.2 ).
5. Write one to the SLEEPDEEP bit in the ARM Cortex-M0+ SCR register.
6. Start the self-wake-up timer by writing a value to the WKT COUNT register
( Table 425 ).
7. Use the ARM WFI instruction.
15.7.7.5 Wake-up from deep power-down mode using the self-wake-up timer:
The part goes through the entire reset process when the self-wake-up timer times out:
1. When the WKT count reaches 0, the following happens:
–
The PMU will turn on the on-chip voltage regulator. When the core voltage reaches
the power-on-reset (POR) trip point, a system reset will be triggered and the chip
re-boots.
–
All registers except the DPDCTRL and GPREG0 to GPREG3 registers and PCON
are in their reset state.
2. Once the chip has booted, read the deep power-down flag in the PCON register
( Table 291 ) to verify that the reset was caused by a wake-up event from deep
power-down and was not a cold reset.
3. Clear the deep power-down flag in the PCON register ( Table 291 ).
4. (Optional) Read the stored data in the general purpose registers ( Section 15.6.2 ).
5. Set up the PMU for the next deep power-down cycle.