UM11029
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User manual
Rev. 1.0 — 16 June 2017
368 of 515
NXP Semiconductors
UM11029
Chapter 20: LPC84x Standard counter/timer (CTIMER)
20.7.11 Count Control Register
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting.
When Counter Mode is chosen as a mode of operation, the CAP input (selected by the
CTCR bits 3:2) is sampled on every rising edge of the APB bus clock. After comparing two
consecutive samples of this CAP input, one of the following four events is recognized:
rising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event occurs and the event corresponds to the one selected by
bits 1:0 in the CTCR register, will the Timer Counter register be incremented.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the APB bus clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input cannot exceed one half of the
APB bus clock. Consequently, duration of the HIGH/LOWLOW levels on the same CAP
input in this case cannot be shorter than 1/APB bus clock.
Bits 7:4 of this register are also used to enable and configure the capture-clears-timer
feature. This feature allows for a designated edge on a particular CAP input to reset the
timer to all zeros. Using this mechanism to clear the timer on the leading edge of an input
pulse and performing a capture on the trailing edge, permits direct pulse-width
measurement using a single capture input without the need to perform a subtraction
operation in software.
Table 381. Count Control Register (CTCR, offset 0x70) bit description
Bit
Symbol
Value
Description
Reset
Value
1:0
CTMODE
Counter/Timer Mode
This field selects which rising APB bus clock edges can increment Timer’s Prescale
Counter (PC), or clear PC and increment Timer Counter (TC).
Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale
Register.
0
0x0
Timer Mode. Incremented every rising APB bus clock edge.
0x1
Counter Mode rising edge. TC is incremented on rising edges on the CAP input
selected by bits 3:2.
0x2
Counter Mode falling edge. TC is incremented on falling edges on the CAP input
selected by bits 3:2.
0x3
Counter Mode dual edge. TC is incremented on both edges on the CAP input selected
by bits 3:2.
3:2
CINSEL
Count Input Select
When bits 1:0 in this register are not 0b00, these bits select which CAP pin is sampled
for clocking.
Note:
If Counter mode is selected in the CTCR, the 3 bits for that input in the Capture
Control Register (CCR) must be programmed as 000. However, capture and/or interrupt
can be selected for the other 3 CAPn inputs in the same timer.
0
0x0
Channel 0. CAP0
0x1
Channel 1. CAP1
0x2
Channel 2. CAP2
0x3
Channel 3. CAP3, not used
4
ENCC
-
Setting this bit to 1 enables clearing of the timer and the prescaler when the
capture-edge event specified in bits 7:5 occurs.
0
