UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
260 of 515
16.1 How to read this chapter
The DMA controller is available on all parts.
16.2 Features
•
25 channels supported with 25 channels connected to peripheral request inputs and
outputs of the USART, SPI, I
2
C, and DAC.
•
DMA operations can be triggered by on- or off-chip events. Each DMA channel can
select one trigger input from 13 sources.
•
Priority is user selectable for each channel.
•
Continuous priority arbitration.
•
Address cache with four entries.
•
Efficient use of data bus.
•
Supports single transfers up to 1,024 words.
•
Address increment options allow packing and/or unpacking data.
16.3 Basic configuration
Configure the DMA as follows:
•
Use the SYSAHBCLKCTRL register (
) to enable the clock to the DMA
registers interface.
•
The DMA interrupt is connected to slot #20 in the NVIC.
•
Each DMA channel has one DMA request line associated and can also select one of
13 input triggers through the input multiplexer registers DMA_ITRIG_INMUX[0:24].
•
Trigger outputs are connected to DMA_INMUX_INMUX[0:3] as inputs to DMA
triggers.
For details on the trigger input and output multiplexing, see
16.3.1 Hardware triggers
Each DMA channel can use one trigger that is independent of the request input for this
channel. The trigger input is selected in the DMA_ITRIG_INMUX registers. There are 13
possible internal trigger sources for each channel with each trigger signal issued by the
output of a peripheral. In addition, the DMA trigger output can be routed to the trigger
input of another channel through the trigger input multiplexing. See
.
See
for the connection of input multiplexers to DMA channels.
See
for a list of possible trigger input sources.
UM11029
Chapter 16: LPC84x DMA controller
Rev. 1.0 — 16 June 2017
User manual
