UM11029
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User manual
Rev. 1.0 — 16 June 2017
284 of 515
NXP Semiconductors
UM11029
Chapter 17: LPC84x USART0/1/2/3/4
•
Configure the USART clock and baud rate. See
•
Send and receive lines are connected to DMA request lines. See
.
For wake-up from deep-sleep and power-down modes the USART must be configured in
synchronous mode. See
for details.
17.3.1 Configure the USART clock and baud rate
All five USARTs have a separate clock selection that include two shared fractional
dividers. The peripheral clock and the fractional divider for the baud rate calculation are
set up in the SYSCON block as follows (see
1. If a fractional value is needed to obtain a particular baud rate, program the fractional
divider. The fractional divider value is the fraction of MULT/DIV. The MULT and DIV
values are programmed in the FRGCTRL register. The DIV value must be
programmed with the fixed value of 256.
FCLK = (FRGINPUTCLK)/(1+(MULT/DIV))
The following rules apply for MULT and DIV:
–
Always set DIV to 256 by programming the FRGCTRL register with the value of
0xFF.
–
Set the MULT to any value between 0 and 255.
2. In asynchronous mode: Configure the baud rate divider BRGVAL in the USARTn BRG
register. The baud rate divider divides the FCLK clock to create the clock needed to
produce the required baud rate.
baud rate = FCLK/((1) x (1)).
BRGVAL = FCLK/(( 1) x baud rate) – 1
(assumes FCLK
oversample rate x baud rate)
Section 17.6.9 “USART Baud Rate Generator register”
3. In synchronous mode: The serial clock is Un_SCLK = FCLK/(1).
