Preliminary User’s Manual U16846EJ1V0UD
311
CHAPTER 17 CLOCK MONITOR
17.1 Functions of Clock Monitor
The clock monitor samples the high-speed system clock using the on-chip Ring-OSC, and generates an internal
reset signal when the high-speed system clock is stopped.
When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set
to 1. For details of RESF, see CHAPTER 16 RESET FUNCTION.
The clock monitor automatically stops under the following conditions.
•
Reset is released and during the oscillation stabilization time
•
In STOP mode and during the oscillation stabilization time
•
When the high-speed system clock is stopped by software (MSTOP = 1 or MCC = 1) and during the oscillation
stabilization time
•
When the Ring-OSC clock is stopped
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
17.2 Configuration of Clock Monitor
The clock monitor includes the following hardware.
Table 17-1. Configuration of Clock Monitor
Item Configuration
Control register
Clock monitor mode register (CLM)
Figure 17-1. Block Diagram of Clock Monitor
Operation mode
controller
High-speed system clock
Ring-OSC clock
CLME
Clock monitor
mode register (CLM)
Internal bus
High-speed system
clock oscillation
monitor circuit
Internal reset
signal
High-speed system clock oscillation
control signal (MSTOP)
High-speed system clock oscillation
stabilization status (OSTC overflow)
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
OSTC: Oscillation stabilization time counter status register (OSTC)
