CHAPTER 8 8-BIT TIMERS H0 AND H1
Preliminary User’s Manual U16846EJ1V0UD
163
8.4 Operation of 8-Bit Timers H0 and H1
8.4.1 Operation as interval timer/square-wave output
When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is
generated and 8-bit timer counter Hn is cleared to 00H.
Compare register 1n (CMP1n) is not used in interval timer mode. Since a match of 8-bit timer counter Hn and the
CMP1n register is not detected even if the CMP1n register is set, timer output is not affected.
By setting bit 0 (TOENn) of timer H mode register n (TMHMDn) to 1, a square wave of any frequency (duty = 50%)
is output from TOHn.
(1) Usage
Generates the INTTMHn signal repeatedly at the same interval.
<1> Set each register.
Figure 8-8. Register Setting During Interval Timer/Square-Wave Output Operation
(i) Setting timer H mode register n (TMHMDn)
0
0/1
0/1
0/1
0
0
0/1
0/1
TMMDn0 TOLEVn
TOENn
CKSn1
CKSn2
TMHEn
TMHMDn
CKSn0
TMMDn1
Timer output setting
Timer output level inversion setting
Interval timer mode setting
Count clock (f
CNT
) selection
Count operation stopped
(ii) CMP0n register setting
•
Compare value (N)
<2> Count operation starts when TMHEn = 1.
<3> When the values of 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is generated
and 8-bit timer counter Hn is cleared to 00H.
Interval time = (N +1)/f
CNT
<4> Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, set
TMHEn to 0.
Remark n = 0, 1
