CHAPTER 17 CLOCK MONITOR
Preliminary User’s Manual U16846EJ1V0UD
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17.4 Operation of Clock Monitor
This section explains the functions of the clock monitor. The monitor start and stop conditions are as follows.
<Monitor start condition>
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to operation enabled (1).
< Monitor stop condition>
•
Reset is released and during the oscillation stabilization time
•
In STOP mode and during the oscillation stabilization time
•
When the high-speed system clock is stopped by software (MSTOP = 1 or MCC = 1) and during the oscillation
stabilization time
•
When the Ring-OSC clock is stopped
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
Table 17-2. Operation Status of Clock Monitor (When CLME = 1)
CPU Operation Clock Operation
Mode High-Speed System Clock
Status
Ring-OSC Clock Status
Clock Monitor Status
Oscillating
STOP mode
Stopped
Stopped
Note
Oscillating
RESET input
Stopped
Note
Stopped
Oscillating Operating
High-speed system
clock
Normal operation
mode
HALT mode
Oscillating
Stopped
Note
Stopped
STOP mode
RESET input
Stopped Oscillating
Stopped
Oscillating
Operating
Ring-OSC clock
Normal operation
mode
HALT mode
Stopped
Stopped
Note The Ring-OSC clock is stopped only when the “Ring-OSC can be stopped by software” is selected by the
option byte. If “Ring-OSC cannot be stopped” is selected, the Ring-OSC clock cannot be stopped.
The clock monitor timing is as shown in Figure 17-3.
