CHAPTER 8 8-BIT TIMERS H0 AND H1
Preliminary User’s Manual U16846EJ1V0UD
161
Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the
Ring-OSC oscillator is divided and supplied as the count clock. If the count clock is the
Ring-OSC clock, the operation of 8-bit timer H0 is not guaranteed.
2. When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited.
3. In the PWM output mode, be sure to set 8-bit timer H compare register 10 (CMP10) when
starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped
(TMHE0 = 0) (be sure to set again even if setting the same value to CMP10).
Remarks 1. f
X
: High-speed system clock oscillation frequency
2. Figures in parentheses apply to operation at f
X
= 10 MHz
3.
TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50)
TMC501: Bit 1 of TMC50
Figure 8-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1)
TMHE1
Stops timer count operation (counter is cleared to 0)
Enables timer count operation (count operation started by inputting clock)
TMHE1
0
1
Timer operation enable
TMHMD1
Symbol
CKS12
CKS11
CKS10
TMMD11 TMMD10 TOLEV1
TOEN1
Address: FF6CH After reset: 00H R/W
f
X
f
X
/2
2
f
X
/2
4
f
X
/2
6
f
X
/2
12
f
R
/2
7
CKS12
0
0
0
0
1
1
CKS11
0
0
1
1
0
0
CKS10
0
1
0
1
0
1
(10 MHz)
(2.5 MHz)
(625 kHz)
(156.25 kHz)
(2.44 kHz)
(1.88 kHz (TYP.))
Count clock (f
CNT
) selection
Note
Setting prohibited
Other than above
Interval timer mode
PWM output mode
Setting prohibited
TMMD11
0
1
TMMD10
0
0
Timer operation mode
Low level
High level
TOLEV1
0
1
Timer output level control (in default mode)
Disables output
Enables output
TOEN1
0
1
Timer output control
Other than above
<7>
6
5
4
3
2
<1>
<0>
Note Be sure to set the count clock so that the following condition is satisfied.
•
V
DD
= 4.0 to 5.5 V: Count clock
≤
10 MHz
•
V
DD
= 3.3 to 4.0 V: Count clock
≤
8.38 MHz
•
V
DD
= 2.7 to 3.3 V: Count clock
≤
5 MHz
