CHAPTER 8 8-BIT TIMERS H0 AND H1
Preliminary User’s Manual U16846EJ1V0UD
168
(2) Timing
chart
The operation timing in PWM output mode is shown below.
Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are
within the following range.
00H
≤
CMP1n (M) < CMP0n (N)
≤
FFH
Remark n = 0, 1
Figure 8-11. Operation Timing in PWM Output Mode (1/4)
(a) Basic operation
Count clock
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
TOHn
(TOLEVn = 1)
00H 01H
A5H 00H 01H 02H
A5H 00H
A5H 00H
01H 02H
CMP1n
A5H
01H
<1>
<2>
<3>
<4>
<1> The count operation is enabled by setting the TMHEn bit to 1. Start 8-bit timer counter Hn by masking one
count clock to count up. At this time, TOHn output remains inactive (when TOLEVn = 0).
<2> When the values of 8-bit timer counter Hn and the CMP0n register match, the TOHn output level is inverted,
the value of 8-bit timer counter Hn is cleared, and the INTTMHn signal is output.
<3> When the values of 8-bit timer counter Hn and the CMP1n register match, the level of the TOHn output is
returned. At this time, the 8-bit timer counter value is not cleared and the INTTMHn signal is not output.
<4> Setting the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive.
Remark n = 0, 1
