CHAPTER 15 STANDBY FUNCTION
Preliminary User’s Manual U16846EJ1V0UD
295
15.1.2 Registers controlling standby function
The standby function is controlled by the following two registers.
•
Oscillation stabilization time counter status register (OSTC)
•
Oscillation stabilization time select register (OSTS)
Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.
(1) Oscillation stabilization time counter status register (OSTC)
This is the status register of the high-speed system clock oscillation stabilization time counter. If the Ring-OSC
clock is used as the CPU clock, the high-speed system clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction, and
MSTOP (bit 7 of MOC register) = 1 clear OSTC to 00H.
Caution Waiting for the oscillation stabilization time is not required when the external RC oscillation
clock is selected as the high-speed system clock by the option byte. Therefore, the CPU clock
can be switched without reading the OSTC value.
Figure 15-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H After reset: 00H R
Symbol
7 6 5 4 3 2 1 0
OSTC 0
0
0
MOST11
MOST13 MOST14 MOST15 MOST16
Oscillation stabilization time status
MOST11 MOST13 MOST14 MOST15 MOST16
f
XP
= 10 MHz f
XP
= 16 MHz
1 0 0 0 0
2
11
/f
XP
min. 204.8
µ
s min. 128
µ
s min.
1 1 0 0 0
2
13
/f
XP
min. 819.2
µ
s min. 512
µ
s min.
1 1 1 0 0
2
14
/f
XP
min. 1.64 ms min. 1.02 ms min.
1 1 1 1 0
2
15
/f
XP
min. 3.27 ms min. 2.04 ms min.
1 1 1 1 1
2
16
/f
XP
min. 6.55 ms min. 4.09 ms min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
2. If the STOP mode is entered and then released while the Ring-OSC clock is
being used as the CPU clock, set the oscillation stabilization time as follows.
•
Desired OSTC oscillation stabilization time
≤
Oscillation stabilization time
set by OSTS
The oscillation stabilization time counter counts only during the oscillation
stabilization time set by OSTS. Therefore, note that only the statuses during the
oscillation stabilization time set by OSTS are set to OSTC after STOP mode has
been released.
3. The wait time when STOP mode is released does not include the time after
STOP mode release until clock oscillation starts (“a” below) regardless of
whether STOP mode is released by RESET input or interrupt generation.
a
STOP mode release
X1 pin voltage
waveform
Remark f
XP
: High-speed system clock oscillation frequency
