NEC 78K0/KB1+, Preliminary User'S Manual

Page: 209 / 405

CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD78F0102H AND 78F0103H ONLY)
Preliminary User’s Manual U16846EJ1V0UD
209
(3) Baud rate generator control register 0 (BRGC0)
This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter.
BRGC0 can be set by an 8-bit memory manipulation instruction.
RESET input sets this register to 1FH.
Figure 11-4. Format of Baud Rate Generator Control Register 0 (BRGC0)
Address: FF71H After reset: 1FH R/W
Symbol 7 6 5 4 3 2 1 0
BRGC0 TPS01 TPS00 0 MDL04 MDL03 MDL02 MDL01 MDL00
TPS01 TPS00 Base clock (f
XCLK0
) selection
Note 1
0 0 TM50 output
Note 2
0 1 f
X
/2 (5 MHz)
1 0 f
X
/2
3
(1.25 MHz)
1 1 f
X
/2
5
(312.5 kHz)
MDL04 MDL03 MDL02 MDL01 MDL00 k Selection of 5-bit counter
output clock
0 0
× × × ×
Setting prohibited
0 1 0 0 0 8 f
XCLK0
/8
0 1 0 0 1 9 f
XCLK0
/9
0 1 0 1 0 10 f
XCLK0
/10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1 1 0 1 0 26 f
XCLK0
/26
1 1 0 1 1 27 f
XCLK0
/27
1 1 1 0 0 28 f
XCLK0
/28
1 1 1 1 0 30 f
XCLK0
/30
1 1 1 1 1 31 f
XCLK0
/31
Notes 1. Be sure to set the base clock so that the following condition is satisfied.
•
V
DD
= 4.0 to 5.5 V: Base clock
≤
10 MHz
•
V
DD
= 3.3 to 4.0 V: Base clock
≤
8.38 MHz
•
V
DD
= 2.7 to 3.3 V: Base clock
≤
5 MHz
2. To select the TM50 output as the base clock, start an operation by setting 8-bit timer/event counter 50
so that the duty is 50% of the output in the PWM mode (bit 6 (TMC506) of the TMC50 register = 1),
and then clear TPS01 and TPS00 to 0. It is not necessary to enable the TO50 pin as a timer output pin
(bit 0 (TOE50) of the TMC register may be 0 or 1).