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NEC 78K0/KB1+, Preliminary User'S Manual


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CHAPTER  13   SERIAL  INTERFACE  CSI10 

Preliminary User’s Manual  U16846EJ1V0UD 

272 

Figure 13-5.  Timing in 3-Wire Serial I/O Mode (2/2)  

 

(2)  Transmission/reception timing (Type 2;  TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 1) 

 

ABH

56H

ADH

5AH

B5H

6AH

D5H

SCK10

SOTB10

SIO10

CSOT10

CSIIF10

SO10

SI10 (input AAH)

AAH

55H (communication data)

55H is written to SOTB10.

Read/write trigger

INTCSI10

 

 

Summary of Contents for 78K0/KB1+

Page 1: ...Document No U16846EJ1V0UD00 1st edition Date Published November 2003 N CP K Printed in Japan PD78F0101H PD78F0102H PD78F0103H 78K0 KB1 8 Bit Single Chip Microcontrollers Preliminary User s Manual 2003...

Page 2: ...Preliminary User s Manual U16846EJ1V0UD 2 MEMO...

Page 3: ...olar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is conside...

Page 4: ...acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics...

Page 5: ...l Branch Seoul Korea Tel 02 558 3737 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 6841 1138 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 NEC Electronics Singapore Pte Ltd Noven...

Page 6: ...al block functions Interrupts Other on chip peripheral functions Electrical specifications target CPU functions Instruction set Explanation of each instruction How to Read This Manual It is assumed th...

Page 7: ...z operation Note This value may change after evaluation Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not mark...

Page 8: ...Document No SEMICONDUCTOR SELECTION GUIDE Products and Packages X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability...

Page 9: ...120 port 12 30 2 2 6 P130 port 13 31 2 2 7 AVREF 31 2 2 8 AVSS 31 2 2 9 RESET 31 2 2 10 X1 and X2 31 2 2 11 CL1 and CL2 31 2 2 12 VDD 31 2 2 13 VSS 31 2 2 14 FLMD0 and FLMD1 31 2 3 Pin I O Circuits an...

Page 10: ...RATOR 82 5 1 Functions of Clock Generator 82 5 2 Configuration of Clock Generator 82 5 3 Registers Controlling Clock Generator 84 5 4 System Clock Oscillator 91 5 4 1 High speed system clock oscillato...

Page 11: ...nd H1 159 8 4 Operation of 8 Bit Timers H0 and H1 163 8 4 1 Operation as interval timer square wave output 163 8 4 2 Operation as PWM output mode 166 CHAPTER 9 WATCHDOG TIMER 172 9 1 Functions of Watc...

Page 12: ...generator 256 CHAPTER 13 SERIAL INTERFACE CSI10 263 13 1 Functions of Serial Interface CSI10 263 13 2 Configuration of Serial Interface CSI10 263 13 3 Registers Controlling Serial Interface CSI10 265...

Page 13: ...20 OPTION BYTE 332 CHAPTER 21 FLASH MEMORY 333 21 1 Internal Memory Size Switching Register 334 21 2 Writing with Flash Programmer 335 21 3 Programming Environment 339 21 4 Communication Mode 339 21 5...

Page 14: ...A DEVELOPMENT TOOLS 388 A 1 Software Package 392 A 2 Language Processing Software 393 A 3 Control Software 394 A 4 Flash Memory Writing Tools 394 A 5 Debugging Tools Hardware 395 A 5 1 When using in...

Page 15: ...ramming with boot swap function On chip power on clear POC circuit and low voltage detector LVI Short startup is possible via the CPU default start using the on chip Ring OSC On chip clock monitor fun...

Page 16: ...AV equipment PC peripheral equipment keyboards etc Household electrical appliances Outdoor air conditioner units Microwave ovens electric rice cookers Industrial equipment Pumps Vending machines FA F...

Page 17: ...0103H Caution Connect the AVSS pin to VSS Remark Items in brackets are the pin names when external RC oscillation is used Pin Identification ANI0 to ANI3 Analog input AVREF Analog reference voltage CL...

Page 18: ...r supply flash memory 32 KB RAM 1 KB Single power supply flash memory 24 KB RAM 1 KB Single power supply flash memory 16 KB RAM 512 B 78K0 KD1 PD78F0123H PD78F0124H HDNote PD78F0122H Two power supply...

Page 19: ...54 CMOS input 4 8 CMOS output 1 Port N ch open drain I O 4 16 bits TM0 1 ch 2 ch 1 ch 2 ch 8 bits TM5 1 ch 2 ch 8 bits TMH 2 ch For watch 1 ch Timer WDT 1 ch 3 wire CSI Note 1 ch 2 ch 1 ch 2 ch Automa...

Page 20: ...ch For watch 1 ch Timer WDT 1 ch 3 wire CSI Note 2 1 ch 2 ch Automatic transmit receive 3 wire CSI 1 ch UART Note 2 1 ch Serial interface UART supporting LIN bus 1 ch 10 bit A D converter 4 ch 8 ch E...

Page 21: ...PD703211Y PD703211 Mask ROM 256 KB RAM 12 KB V850ES KF1 PD70F3308Y PD70F3308 Single power supply flash memory 256 KB RAM 12 KB PD703308Y PD703308 Mask ROM 256 KB RAM 12 KB PD703214Y PD703214 Mask ROM...

Page 22: ...h 1 ch 1 ch For watch 1 ch 1 ch 1 ch 1 ch WDT1 1 ch 1 ch 1 ch 1 ch Timer WDT2 1 ch 1 ch 1 ch 1 ch RTO 6 bits 1 ch 6 bits 1 ch 6 bits 1 ch 6 bits 2 ch CSI 2 ch 2 ch 2 ch 3 ch Automatic transmit receive...

Page 23: ...Timer WDT2 1 ch 1 ch 1 ch 1 ch RTO 6 bits 1 ch 6 bits 1 ch 6 bits 1 ch 6 bits 2 ch CSI 2 ch 2 ch 2 ch 3 ch Automatic transmit receive 3 wire CSI 1 ch 2 ch 2 ch UART 1 ch 1 ch 1 ch 2 ch UART supporting...

Page 24: ...al high speed RAM Flash memory Port 0 P00 to P03 4 Port 1 P10 to P17 Port 2 P20 to P23 4 Port 3 P30 to P33 4 Port 12 P120 Port 13 P130 System control RESET X1 CL1 X2 CL2 RxD0Note P11 TxD0Note P10 Seri...

Page 25: ...nipulate set reset test and Boolean operation BCD adjust etc I O ports Total 22 CMOS I O 17 CMOS input 4 CMOS output 1 Timers 16 bit timer event counter 1 channel 8 bit timer event counter 1 channel 8...

Page 26: ...50 TMH0 TMH1 Watchdog Timer Interval timer 1 channel 1 channel 1 channel 1 channel 1 channel Operation mode External event counter 1 channel 1 channel Timer output 1 output 1 output 1 output 1 output...

Page 27: ...Input P10 SCK10 TxD0 Note P11 SI10 RxD0 Note P12 SO10 P13 TxD6 P14 RxD6 P15 TOH0 P16 TOH1 INTP5 P17 I O Port 1 8 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up re...

Page 28: ...event counter 00 P00 TI010 Input Capture trigger input to capture register CR000 of 16 bit timer event counter 00 Input P01 TO00 TO00 Output 16 bit timer event counter 00 output Input P01 TI010 TI50 I...

Page 29: ...ster CR000 of 16 bit timer event counter 00 c TO00 This is a timer output pin 2 2 2 P10 to P17 port 1 P10 to P17 function as an 8 bit I O port These pins also function as pins for external interrupt r...

Page 30: ...these pins as analog input pins see 5 ANI0 P20 to ANI3 P23 in 10 6 Cautions for A D Converter 2 2 4 P30 to P33 port 3 P30 to P33 function as a 4 bit I O port These pins also function as pins for exte...

Page 31: ...ive low system reset input pin 2 2 10 X1 and X2 These are the pins for connecting a resonator for high speed system clock oscillation When supplying an external clock input a signal to the X1 pin and...

Page 32: ...K10 TxD0 Note P11 SI10 RxD0 Note 8 A P12 SO10 P13 TxD6 5 A P14 RxD6 8 A P15 TOH0 5 A P16 TOH1 INTP5 P17 TI50 TO50 FLMD1 8 A I O Input Independently connect to VDD or VSS via a resistor Output Leave op...

Page 33: ...ype 8 A Type 5 A Type 9 C Schmitt triggered input with hysteresis characteristics IN Pull up enable Data Output disable VDD P ch VDD P ch IN OUT N ch VDD P ch N ch Data OUT IN Comparator VREF threshol...

Page 34: ...n the 78K0 KB1 are fixed IMS CFH Therefore set the value corresponding to each product as indicated below In addition set the following values to the internal memory size switching register IMS when u...

Page 35: ...egisters 32 8 bits Reserved Flash memory 8192 8 bits Program memory space Data memory space Vector table area H CALLT table area Program area CALLF entry area Program area 0 0 0 0 H F 3 0 0 H 0 4 0 0...

Page 36: ...egisters 32 8 bits Reserved Flash memory 16384 8 bits Program memory space Data memory space Vector table area CALLT table area Program area CALLF entry area Program area H 0 0 0 0 H F 3 0 0 H 0 4 0 0...

Page 37: ...egisters 32 8 bits Reserved Flash memory 24576 8 bits Program memory space Data memory space Vector table area CALLT table area Program area CALLF entry area Program area H 0 0 0 0 H F 3 0 0 H 0 4 0 0...

Page 38: ...the vector table area Of the 16 bit address the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses Table 3 3 Vector Table Vector Table Address Interrupt Source...

Page 39: ...H to FEFFH is assigned to four general purpose register banks consisting of eight 8 bit registers per bank This area cannot be used as a program area in which instructions are written and executed The...

Page 40: ...of special function registers SFR and general purpose registers are available for use Figures 3 4 to 3 6 show the correspondence between data memory and addressing For details of each addressing mode...

Page 41: ...direct addressing SFR addressing Internal high speed RAM 768 8 bits General purpose registers 32 8 bits Reserved Flash memory 16384 8 bits Register addressing Direct addressing Register indirect addr...

Page 42: ...direct addressing SFR addressing Internal high speed RAM 768 8 bits General purpose registers 32 8 bits Reserved Register addressing Direct addressing Register indirect addressing Based addressing Ba...

Page 43: ...PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 2 Program status word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruction execution Program status...

Page 44: ...refer to 14 3 3 Priority specification flag registers PR0L PR0H PR1L can not be acknowledged Actual request acknowledgment is controlled by the interrupt enable flag IE f Carry flag CY This flag store...

Page 45: ...PUSH rp instruction when SP FEE0H Register pair lower FEE0H SP SP FEE0H FEDFH FEDEH Register pair upper FEDEH b CALL CALLF CALLT instructions when SP FEE0H PC15 PC8 FEE0H SP SP FEE0H FEDFH FEDEH PC7...

Page 46: ...ack Memory a POP rp instruction when SP FEDEH Register pair lower FEE0H SP SP FEE0H FEDFH FEDEH Register pair upper FEDEH b RET instruction when SP FEDEH PC15 PC8 FEE0H SP SP FEE0H FEDFH FEDEH PC7 PC0...

Page 47: ...s X A C B E D L H AX BC DE and HL and absolute names R0 to R7 and RP0 to RP3 Register banks to be used for instruction execution are set by the CPU control instruction SEL RBn Because of the 4 registe...

Page 48: ...e 8 bit manipulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved by the assembler for the 16 bit manipulation instr...

Page 49: ...50 R 00H FF17H 8 bit timer compare register 50 CR50 R W 00H FF18H 8 bit timer H compare register 00 CMP00 R W 00H FF19H 8 bit timer H compare register 10 CMP10 R W 00H FF1AH 8 bit timer H compare regi...

Page 50: ...gister 0 Note 1 ASIM0 R W 01H FF71H Baud rate generator control register 0 Note 1 BRGC0 R W 1FH FF72H Receive buffer register 0 Note 1 RXB0 R FFH FF73H Asynchronous serial interface reception error st...

Page 51: ...6H Interrupt mask flag register 1L MK1L R W FFH FFE8H Priority specification flag register 0L PR0 PR0L R W FFH FFE9H Priority specification flag register 0H PR0H R W FFH FFEAH Priority specification f...

Page 52: ...ative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the pro...

Page 53: ...n the CALL addr16 or BR addr16 or CALLF addr11 instruction is executed CALL addr16 and BR addr16 instructions can be branched to the entire memory space The CALLF addr11 instruction is branched to the...

Page 54: ...ecuted This instruction references the address stored in the memory table from 40H to 7FH and allows branching to the entire memory space Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory Table...

Page 55: ...ction Register to Be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for...

Page 56: ...ollowing operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L...

Page 57: ...sed with immediate data in an instruction word becoming an operand address Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting add...

Page 58: ...er event counter are mapped in this area allowing SFRs to be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is cleared to...

Page 59: ...FF00H to FFCFH and FFE0H to FFFFH However the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 1...

Page 60: ...ct flag RBS0 and RBS1 serve as an operand address for addressing the memory This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example...

Page 61: ...nd RBS1 and the sum is used to address the memory Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried...

Page 62: ...flag RBS0 and RBS1 and the sum is used to address the memory Addition is performed by expanding the B or C register contents as a positive number to 16 bits A carry from the 16th bit is ignored This...

Page 63: ...s automatically employed when the PUSH POP subroutine call and return instructions are executed or the register is saved reset upon generation of an interrupt request With stack addressing only the in...

Page 64: ...ding Pins AVREF P20 to P23 VDD Pins other than P20 to P23 78K0 KB1 products are provided with the ports shown in Figure 4 1 which enable variety of control operations The functions of each port are sh...

Page 65: ...rt Input ANI0 to ANI3 P30 to P33 I O Port 3 4 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input INTP1 to INTP4 P...

Page 66: ...se of an on chip pull up resistor can be specified in 1 bit units by pull up resistor option register 0 PU0 This port can also be used for timer I O RESET input sets port 0 to input mode Figures 4 2 t...

Page 67: ...Figure 4 3 Block Diagram of P01 P01 TI010 TO00 WRPU RD WRPORT WRPM PU01 Alternate function Output latch P01 PM01 PU0 PM0 Alternate function VDD P ch Selector Internal bus PU0 Pull up resistor option...

Page 68: ...46EJ1V0UD 68 Figure 4 4 Block Diagram of P02 and P03 WRPU RD WRPORT WRPM PU02 PU03 Output latch P02 P03 PM02 PM03 PU0 PM0 VDD P ch P02 P03 Selector Internal bus PU0 Pull up resistor option register 0...

Page 69: ...erial interface data I O clock I O and timer I O and flash memory programming mode setting RESET input sets port 1 to input mode Figures 4 5 to 4 9 show block diagrams of port 1 Caution When using P10...

Page 70: ...and P14 P11 SI10 RxD0Note P14 RxD6 WRPU RD WRPORT WRPM PU11 PU14 Alternate function Output latch P11 P14 PM11 PM14 PU1 PM1 VDD P ch Selector Internal bus Note Available only in the PD78F0102H and 78F0...

Page 71: ...gure 4 7 Block Diagram of P12 and P15 P12 SO10 P15 TOH0 WRPU RD WRPORT WRPM PU12 PU15 Output latch P12 P15 PM12 PM15 PU1 PM1 Alternate function VDD P ch Selector Internal bus PU1 Pull up resistor opti...

Page 72: ...846EJ1V0UD 72 Figure 4 8 Block Diagram of P13 P13 TxD6 WRPU RD WRPORT WRPM PU13 Output latch P13 PM13 PU1 PM1 Alternate function VDD P ch Internal bus Selector PU1 Pull up resistor option register 1 P...

Page 73: ...gram of P16 and P17 P16 TOH1 INTP5 P17 TI50 TO50 FLMD1 WRPU RD WRPORT WRPM PU16 PU17 Alternate function Output latch P16 P17 PM16 PM17 PU1 PM1 Alternate function VDD P ch Selector Internal bus PU1 Pul...

Page 74: ...0UD 74 4 2 3 Port 2 Port 2 is a 4 bit input only port This port can also be used for A D converter analog input Figure 4 10 shows a block diagram of port 2 Figure 4 10 Block Diagram of P20 to P23 RD A...

Page 75: ...or can be specified in 1 bit units by pull up resistor option register 3 PU3 This port can also be used for external interrupt request input RESET input sets port 3 to input mode Figure 4 11 shows a b...

Page 76: ...n on chip pull up resistor can be specified by pull up resistor option register 12 PU12 This port can also be used for external interrupt input RESET input sets port 12 to input mode Figure 4 12 shows...

Page 77: ...ummy output as the reset signal to the CPU 4 3 Registers Controlling Port Function Port functions are controlled by the following three types of registers Port mode registers PM0 PM1 PM3 PM12 Port reg...

Page 78: ...1 Input mode output buffer off Table 4 4 Settings of Port Mode Register and Output Latch When Alternate Function Is Used Alternate Function Pin Name Name I O PM P P00 TI000 Input 1 TI010 Input 1 P01...

Page 79: ...but P2 is undefined Figure 4 15 Format of Port Register 7 0 Symbol P0 6 0 5 0 4 0 3 P03 2 P02 1 P01 0 P00 Address FF00H After reset 00H output latch R W R W 7 P17 P1 6 P16 5 P15 4 P14 3 P13 2 P12 1 P1...

Page 80: ...bits used as alternate function output pins regardless of the settings of PU0 PU1 PU3 and PU12 These registers can be set by a 1 bit or 8 bit memory manipulation instruction RESET input clears these r...

Page 81: ...ue is written to the output latch by a transfer instruction but since the output buffer is off the pin status does not change Once data is written to the output latch it is retained until data is writ...

Page 82: ...ain OSC control register MOC Ring OSC oscillator The Ring OSC oscillator oscillates a clock of fR 240 kHz TYP Oscillation can be stopped by setting the Ring OSC mode register RCM when Can be stopped b...

Page 83: ...signal CPU clock fCPU fCPU Processor clock control register PCC PCC2 MCM0 MCS Main clock mode register MCM OSTS1 OSTS0 OSTS2 Oscillation stabilization time counter Oscillation stabilization time sele...

Page 84: ...a 1 bit or 8 bit memory manipulation instruction RESET input clears this register to 00H Figure 5 2 Format of Processor Clock Control Register PCC Address FFFBH After reset 00H R W Symbol 7 6 5 4 3 2...

Page 85: ...otes 1 The main clock mode register MCM is used to set the CPU clock high speed system clock Ring OSC clock see Figure 5 4 2 When crystal ceramic oscillation is used 2 Ring OSC mode register RCM This...

Page 86: ...clock is selected as the clock to be supplied to the CPU the divided clock of the Ring OSC oscillator output fX is supplied to the peripheral hardware fX 240 kHz TYP Operation of the peripheral hardwa...

Page 87: ...h speed system clock oscillator operating 1 High speed system clock oscillator stopped Caution Make sure that bit 1 MCS of the main clock mode register MCM is 0 before setting MSTOP 5 Oscillation stab...

Page 88: ...set to 1 in order from MOST11 and remain 1 2 If the STOP mode is entered and then released while the Ring OSC clock is being used as the CPU clock set the oscillation stabilization time as follows Des...

Page 89: ...STS0 fXP 10 MHz fXP 16 MHz 0 0 1 2 11 fXP 204 8 s 128 s 0 1 0 2 13 fXP 819 2 s 512 s 0 1 1 2 14 fXP 1 64 ms 1 02 ms 1 0 0 2 15 fXP 3 27 ms 2 04 ms 1 0 1 2 16 fXP 6 55 ms 4 09 ms Other than above Setti...

Page 90: ...5 8 Format of System Wait Control Register VSWC 0 Symbol VSWC 0 0 PAW0 0 0 0 PDW0 Address FFFDH After reset 00H R W PDW0 0 No wait One wait state inserted 1 Control of system clock data wait PAW0 0 N...

Page 91: ...n and input the inverse signal to the X2 pin Figure 5 9 shows the external circuit of the crystal ceramic oscillator Figure 5 9 External Circuit of Crystal Ceramic Oscillator a Crystal ceramic oscilla...

Page 92: ...onator Connection a Too long wiring b Crossed signal line X2 VSS X1 X1 VSS X2 PORT c Wiring near high alternating current d Current flowing through ground line of oscillator potential at points A B an...

Page 93: ...lation b External clock VSS CL1 CL2 R C External clock CL1 CL2 Caution When using the external RC oscillator wire as follows in the area enclosed by the broken lines in Figure 5 11 to avoid an adverse...

Page 94: ...tor Connection a Too long wiring b Crossed signal line CL2 CL1 VSS CL2 PORT CL1 VSS c Wiring near high fluctuating current d Current flowing through ground line of oscillator potential at points A and...

Page 95: ...cks and controls the operation modes of the CPU such as standby mode High speed system clock fXP Ring OSC clock fR CPU clock fCPU Clock to peripheral hardware The CPU starts operation when the on chip...

Page 96: ...of the high speed system clock and Ring OSC clock is stopped b After RESET release the CPU clock can be switched from the Ring OSC clock to the high speed system clock using bit 0 MCM0 of the main cl...

Page 97: ...CM0 0 MCM0 1Note 2 MSTOP 1Note 3 MSTOP 0 HALT instruction HALT instruction HALT instruction STOPNote 4 ResetNote 5 Notes 1 When shifting from status 3 to status 4 make sure that bit 1 MCS of the main...

Page 98: ...ck oscillation stabilization time status using the oscillation stabilization time counter status register OSTC Waiting for the oscillation stabilization time is not required when the external RC oscil...

Page 99: ...SC by the option byte 3 Operates using the CPU clock at STOP instruction execution 4 Operates using the CPU clock at HALT instruction execution Caution The RSTOP setting is valid only when Can be stop...

Page 100: ...ssor clock control register 2 fXP High speed system clock oscillation frequency 3 fR Ring OSC clock oscillation frequency 4 The maximum time is the number of clocks of the CPU clock before switching 5...

Page 101: ...0H MCM 00H MOC 00H OSTC 00H OSTS 05HNote OSTC checkNote Each processing After reset release PCC setting MCM 0 1 High speed system clock operation Ring OSC clock operation dividing set PCC Register ini...

Page 102: ...MCM 1 MCS is changed from 1 to 0 Ring OSC clock operation Ring OSC oscillating Ring OSC clock operation High speed system clock operation No RSTOP 0 Yes RSTOP 1 MCM 03H RCM 0Note RSTOP 1 RSTOP 0 MCM0...

Page 103: ...egister MCM Register fCPU Mode MCM0 MSTOP RSTOP Note 1 MCS Ring OSC oscillating 1 0 0 1 High speed system clock Note 2 Ring OSC stopped 1 0 1 1 High speed system clock oscillating 0 0 0 0 Ring OSC clo...

Page 104: ...interval 2 PPG output 16 bit timer event counter 00 can output a rectangular wave whose frequency and output pulse width can be set freely 3 Pulse width measurement 16 bit timer event counter 00 can m...

Page 105: ...00 PRM00 Port mode register 0 PM0 Port register 0 P0 Figure 6 1 shows the block diagram Figure 6 1 Block Diagram of 16 Bit Timer Event Counter 00 Internal bus Capture compare control register 00 CRC0...

Page 106: ...apture compare register 000 CR000 CR000 is a 16 bit register that has the functions of both a capture register and a compare register Whether it is used as a capture register or as a compare register...

Page 107: ...capture compare control register 00 CRC00 Cautions 1 Set a value other than 0000H in CR000 in the mode in which clear start occurs on a match of TM00 and CR000 2 If CR000 is set to 0000H in the free r...

Page 108: ...lid edge of the TI000 pin is set by prescaler mode register 00 PRM00 see Table 6 3 Table 6 3 CR010 Capture Trigger and Valid Edge of TI000 Pin CRC002 1 TI000 Pin Valid Edge CR010 Capture Trigger ES001...

Page 109: ...ler mode register 00 PRM00 Port mode register 0 PM0 Port register 0 P0 1 16 bit timer mode control register 00 TMC00 This register sets the 16 bit timer operating mode the 16 bit timer counter 00 TM00...

Page 110: ...R010 1 1 1 Match between TM00 and CR000 match between TM00 and CR010 or TI000 pin valid edge Generated on match between TM00 and CR000 or match between TM00 and CR010 OVF00 16 bit timer counter 00 TM0...

Page 111: ...CR000 capture trigger selection 0 Captures on valid edge of TI010 pin 1 Captures on valid edge of TI000 pin by reverse phase CRC000 CR000 operating mode selection 0 Operates as compare register 1 Oper...

Page 112: ...0 1 Timer output F F reset 0 1 0 Timer output F F set 1 1 1 Setting prohibited TOC001 Timer output F F control using match of CR000 and TM00 0 Disables inversion operation 1 Enables inversion operatio...

Page 113: ...0 0 PRM001 PRM000 ES101 ES100 TI010 pin valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES001 ES000 TI000 pin valid edge selection 0 0 Fa...

Page 114: ...he TI000 pin or TI010 pin to enable the operation of 16 bit timer counter 00 TM00 Care is therefore required when pulling up the TI000 or TI010 pin However when re enabling operation after the operati...

Page 115: ...the PRM000 register 4 Set the TMC00 register to start the operation see Figure 6 10 for the set value Caution CR000 cannot be rewritten during TM00 operation Remark For how to enable the INTTM000 int...

Page 116: ...apture compare control register 00 CRC00 7 0 6 0 5 0 4 0 3 0 CRC002 0 1 CRC001 0 1 CRC000 0 CRC00 CR000 used as compare register c Prescaler mode register 00 PRM00 ES101 0 1 ES100 0 1 ES001 0 1 ES000...

Page 117: ...VF00 Clear circuit INTTM000 fX fX 22 fX 28 TI000 P00 Selector Noise eliminator fX Note Note OVF00 is set to 1 only when CR000 is set to FFFFH Figure 6 12 Timing of Interval Timer Operation Count clock...

Page 118: ...see Figure 6 13 for the set value 5 Set the count clock by using the PRM00 register 6 Set the TMC00 register to start the operation see Figure 6 13 for the set value Caution To change the value of the...

Page 119: ...TOC004 1 LVS00 0 1 LVR00 0 1 TOC001 1 TOE00 1 TOC00 Enables TO00 output Inverts output on match between TM00 and CR000 Specifies initial value of TO00 output F F setting 11 is prohibited Inverts outpu...

Page 120: ...width M 1 t 1 cycle N 1 t N CR000 capture value CR010 capture value M M N 1 N N Clear Clear Cautions 1 CR000 cannot be rewritten during TM00 operation 2 In the PPG output operation change the pulse w...

Page 121: ...ulse width is sampled in the count clock cycle selected by prescaler mode register 00 PRM00 and the valid level of the TI000 or TI010 pin is detected twice thus eliminating noise with a short pulse wi...

Page 122: ...ected twice thus eliminating noise with a short pulse width Figure 6 17 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register When TI000 and CR010 Ar...

Page 123: ...OVF00 16 bit timer capture compare register 010 CR010 Internal bus INTTM010 Selector Figure 6 19 Timing of Pulse Width Measurement Operation with Free Running Counter and One Capture Register with Bot...

Page 124: ...nd bits 6 and 7 ES100 and ES101 of PRM00 Sampling is performed at the interval selected by prescaler mode register 00 PRM00 and a capture operation is only performed when the valid level of the TI000...

Page 125: ...on with Free Running Counter with Both Edges Specified t 0000H 0000H FFFFH 0001H D0 D0 TI010 pin input CR000 capture value INTTM010 INTTM000 OVF00 D1 D0 t D3 D2 t 10000H D1 D2 t 10000H D1 D2 1 t D1 D2...

Page 126: ...operation is only performed when the valid level of the TI000 pin is detected twice thus eliminating noise with a short pulse width Figure 6 22 Control Register Settings for Pulse Width Measurement wi...

Page 127: ...y means of restart When input of a valid edge to the TI000 pin is detected the count value of 16 bit timer counter 00 TM00 is taken into 16 bit timer capture compare register 010 CR010 and then the pu...

Page 128: ...00 1 CRC00 CR000 used as capture register Captures to CR000 at inverse edge to valid edge of TI000 CR010 used as capture register c Prescaler mode register 00 PRM00 ES101 0 1 ES100 0 1 ES001 0 ES000 1...

Page 129: ...vent counter counts the number of external clock pulses input to the TI000 pin using 16 bit timer counter 00 TM00 TM00 is incremented each time the valid edge specified by prescaler mode register 00 P...

Page 130: ...CR000 b Capture compare control register 00 CRC00 7 0 6 0 5 0 4 0 3 0 CRC002 0 1 CRC001 0 1 CRC000 0 CRC00 CR000 used as compare register c Prescaler mode register 00 PRM00 ES101 0 1 ES100 0 1 ES001 0...

Page 131: ...OVF00Note Noise eliminator 16 bit timer counter 00 TM00 Valid edge of TI000 pin INTTM000 Note OVF00 is set to 1 only when CR000 is set to FFFFH Figure 6 28 External Event Counter Operation Timing wit...

Page 132: ...able the INTTM000 interrupt see CHAPTER 14 INTERRUPT FUNCTIONS A square wave with any selected frequency can be output at intervals determined by the count value preset to 16 bit timer capture compare...

Page 133: ...nvert output on match between TM00 and CR010 Disables one shot pulse output d Prescaler mode register 00 PRM00 ES101 0 1 ES100 0 1 ES001 0 1 ES000 0 1 3 0 2 0 PRM001 0 1 PRM000 0 1 PRM00 Selects count...

Page 134: ...e 6 31 and by setting bit 6 OSPT00 of the TOC00 register to 1 by software By setting the OSPT00 bit to 1 16 bit timer event counter 00 is cleared and started and its output becomes active at the count...

Page 135: ...0 1 0 c 16 bit timer output control register 00 TOC00 0 7 0 1 1 0 1 TOC00 LVR00 LVS00 TOC004 OSPE00 OSPT00 TOC001 TOE00 Enables TO00 output Inverts output upon match between TM00 and CR000 Specifies i...

Page 136: ...t control register 00 TOC00 as shown in Figure 6 33 and by using the valid edge of the TI000 pin as an external trigger The valid edge of the TI000 pin is specified by bits 4 and 5 ES000 ES001 of pres...

Page 137: ...sed as compare register 0 0 1 0 c 16 bit timer output control register 00 TOC00 0 7 0 1 1 0 1 TOC00 LVR00 TOC001 TOE00 OSPE00 OSPT00 TOC004 LVS00 Enables TO00 output Inverts output upon match between...

Page 138: ...pecified 0000H N N N N N M M M M M N 1 N 2 M 1 M 2 M 2 M 1 0001H 0000H Count clock TM00 count value CR010 set value CR000 set value TI000 pin input INTTM010 INTTM000 TO00 pin output When TMC00 is set...

Page 139: ...ounter 00 has been stopped 4 Valid edge setting Set the valid edge of the TI000 pin after setting bits 2 and 3 TMC002 and TMC003 of 16 bit timer mode control register 00 TMC00 to 0 0 respectively and...

Page 140: ...0 INTTM000 FFFFH FFFEH FFFFH 0000H 0001H 2 Even if the OVF00 flag is cleared before the next count clock before TM00 becomes 0001H after the occurrence of TM00 overflow the OVF00 flag is re set newly...

Page 141: ...capture operation is performed at the falling edge of the count clock An interrupt request input INTTM000 INTTM010 however is generated at the rise of the next count clock 10 Compare operation A capt...

Page 142: ...of 8 Bit Timer Event Counter 50 Internal bus 8 bit timer compare register 50 CR50 TI50 TO50 FLMD1 P17 fX 22 fX 26 fX 28 fX 213 fX fX 2 Match Mask circuit OVF Clear 3 Selector TCL502 TCL501 TCL500 Tim...

Page 143: ...er clock selection register 50 TCL50 8 bit timer mode control register 50 TMC50 Port mode register 1 PM1 Port register 1 P1 1 8 bit timer counter 50 TM50 TM50 is an 8 bit register that counts the coun...

Page 144: ...n PWM mode when the TO50 pin becomes high level due to a TM50 overflow and the values of TM50 and CR50 match the TO50 pin becomes inactive The value of CR50 can be set within 00H to FFH RESET input cl...

Page 145: ...L501 TCL500 TCL502 TCL501 TCL500 Count clock selection Note 0 0 0 TI50 pin falling edge 0 0 1 TI50 pin rising edge 0 1 0 fX 10 MHz 0 1 1 fX 2 5 MHz 1 0 0 fX 2 2 2 5 MHz 1 0 1 fX 2 6 156 25 kHz 1 1 0 f...

Page 146: ...5 Format of 8 Bit Timer Mode Control Register 50 TMC50 Address FF6BH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 TMC50 TCE50 TMC506 0 0 LVS50 LVR50 TMC501 TOE50 TCE50 TM50 count operation control 0 Af...

Page 147: ...are read 0 is read 3 The values of the TMC506 LVS50 LVR50 TMC501 and TOE50 bits are reflected at the TO50 pin regardless of the value of TCE50 3 Port mode register 1 PM1 This register sets port 1 inpu...

Page 148: ...imer clock selection register 50 TCL50 Setting 1 Set the registers TCL50 Select the count clock CR50 Compare value TMC50 Stop the count operation select clear start mode entered on a match of TM50 and...

Page 149: ...ure 7 7 Interval Timer Operation Timing 2 2 b When CR50 00H t Interval time Count clock TM50 CR50 TCE50 INTTM50 00H 00H 00H 00H 00H c When CR50 FFH t Count clock TM50 CR50 TCE50 INTTM50 01H FEH FFH 00...

Page 150: ...value of CR50 INTTM50 is generated Setting 1 Set each register Set port mode register 1 PM17 to 1 TCL50 Select TI50 pin edge TI50 pin falling edge TCL50 00H TI50 pin rising edge TCL50 01H CR50 Compare...

Page 151: ...r start mode entered on a match of TM50 and CR50 LVS50 LVR50 Timer Output F F Status Setting 1 0 High level output 0 1 Low level output Timer output F F inversion enabled Timer output enabled TMC50 00...

Page 152: ...and port mode register 1 PM17 to 0 TCL50 Select the count clock CR50 Compare value TMC50 Stop the count operation select PWM mode The timer output F F is not changed timer output is enabled TMC501 Ac...

Page 153: ...3 Inactive level 1 5 t b CR50 00H Count clock TM50 CR50 TCE50 INTTM50 TO50 L Inactive level Inactive level 01H 00H FFH 00H 01H 02H N N 1 FFH 00H 01H 02H M 00H 00H N 2 t c CR50 FFH TM50 Count clock CR5...

Page 154: ...lue is transferred to CR50 at second overflow Count clock TM50 CR50 TCE50 INTTM50 TO50 N N 1 N 2 FFH 00H 01H N N 1 N 2 FFH 00H 01H 02H N 02H N H M M M 1 M 2 1 CR50 change N M 2 t Caution When reading...

Page 155: ...t Timers H0 and H1 8 bit timers H0 and H1 include the following hardware Table 8 1 Configuration of 8 Bit Timers H0 and H1 Item Configuration Timer register 8 bit timer counter Hn Registers 8 bit time...

Page 156: ...OEN0 8 bit timer H mode register 0 TMHMD0 8 bit timer H compare register 10 CMP10 Decoder TOH0 P15 INTTMH0 Selector fX fX 2 fX 22 fX 26 fX 210 Interrupt generator Output controller Level inversion 1 0...

Page 157: ...10 TOLEV1 TOEN1 8 bit timer H mode register 1 TMHMD1 8 bit timer H compare register 11 CMP11 Decoder TOH1 INTP5 P16 INTTMH1 Selector fX fX 22 fX 24 fX 26 fX 212 fR 27 Interrupt generator Output contro...

Page 158: ...8 bit memory manipulation instruction RESET input clears this register to 00H Figure 8 4 Format of 8 Bit Timer H Compare Register 1n CMP1n Symbol CMP1n n 0 1 Address FF19H CMP10 FF1BH CMP11 After rese...

Page 159: ...registers are used to control 8 bit timers H0 and H1 8 bit timer H mode register n TMHMDn Port mode register 1 PM1 Port register 1 P1 1 8 bit timer H mode register n TMHMDn This register controls the...

Page 160: ...0 Timer operation mode Low level High level TOLEV0 0 1 Timer output level control in default mode Disables output Enables output TOEN0 0 1 Timer output control Other than above 7 6 5 4 3 2 1 0 Notes...

Page 161: ...C50 TMC501 Bit 1 of TMC50 Figure 8 6 Format of 8 Bit Timer H Mode Register 1 TMHMD1 TMHE1 Stops timer count operation counter is cleared to 0 Enables timer count operation count operation started by i...

Page 162: ...ed TMHE1 0 be sure to set again even if setting the same value to CMP11 Remarks 1 fX High speed system clock oscillation frequency 2 fR Ring OSC clock oscillation frequency 3 Figures in parentheses ap...

Page 163: ...50 is output from TOHn 1 Usage Generates the INTTMHn signal repeatedly at the same interval 1 Set each register Figure 8 8 Register Setting During Interval Timer Square Wave Output Operation i Setting...

Page 164: ...bit timer counter Hn clear 2 Level inversion match interrupt occurrence 8 bit timer counter Hn clear 3 1 1 The count operation is enabled by setting the TMHEn bit to 1 The count clock starts counting...

Page 165: ...Wave Output Operation 2 2 b Operation when CMP0n FFH 00H Count clock Count start 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn 01H FEH Clear Clear FFH 00H FEH FFH 00H FFH Interval time c Operation w...

Page 166: ...ch an arbitrary duty and arbitrary cycle can be set is output 1 Set each register Figure 8 10 Register Setting in PWM Output Mode i Setting timer H mode register n TMHMDn 0 0 1 0 1 0 1 1 0 0 1 1 TMMDn...

Page 167: ...operation set TMHEn 0 If the setting value of the CMP0n register is N the setting value of the CMP1n register is M and the count clock frequency is fCNT the PWM pulse output cycle and duty are as fol...

Page 168: ...5H 01H 1 2 3 4 1 The count operation is enabled by setting the TMHEn bit to 1 Start 8 bit timer counter Hn by masking one count clock to count up At this time TOHn output remains inactive when TOLEVn...

Page 169: ...when CMP0n FFH CMP1n 00H Count clock 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn TOLEVn 0 00H 01H FFH 00H 01H 02H FFH 00H FFH 00H 01H 02H CMP1n FFH 00H c Operation when CMP0n FFH CMP1n FEH Count c...

Page 170: ...s Manual U16846EJ1V0UD 170 Figure 8 11 Operation Timing in PWM Output Mode 3 4 d Operation when CMP0n 01H CMP1n 00H Count clock 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn TOLEVn 0 01H 00H 01H 00...

Page 171: ...t timer counter Hn is cleared the TOHn output becomes active and the INTTMHn signal is output 4 If the CMP1n register value is changed the value is latched and not transferred to the register When the...

Page 172: ...uring Ring OSC Clock Operation During High Speed System Clock Operation fR 2 11 8 53 ms fXP 2 13 819 2 s fR 2 12 17 07 ms fXP 2 14 1 64 ms fR 2 13 34 13 ms fXP 2 15 3 28 ms fR 2 14 68 27 ms fXP 2 16 6...

Page 173: ...The watchdog timer can be stopped in standby mode Note 2 Notes 1 As long as power is being supplied Ring OSC oscillation cannot be stopped except in the reset period 2 The conditions under which clock...

Page 174: ...ounter or fXP 213 to fXP 220 fR 211 to fR 218 Watchdog timer enable register WDTE Watchdog timer mode register WDTM 3 3 2 Clear Option byte to set Ring OSC cannot be stopped or Ring OSC can be stopped...

Page 175: ...alue is written 2 Reset is released at the maximum cycle WDCS2 1 0 1 1 1 Cautions 1 If data is written to WDTM a wait cycle is generated For details see CHAPTER 25 CAUTIONS FOR WAIT 2 Set bits 7 6 and...

Page 176: ...en the watchdog timer operation and the internal reset signal generated by the watchdog timer is shown below Table 9 4 Relationship Between Watchdog Timer Operation and Internal Reset Signal Generated...

Page 177: ...mer mode register WDTM by an 8 bit memory manipulation instructionNotes 1 2 Cycle Set using bits 2 to 0 WDCS2 to WDCS0 3 After the above procedures are executed writing ACH to WDTE clears the count to...

Page 178: ...lock fXP Watchdog timer operation stopped Cycle Set using bits 2 to 0 WDCS2 to WDCS0 3 After the above procedures are executed writing ACH to WDTE clears the count to 0 enabling recounting Notes 1 As...

Page 179: ...Figure 9 4 Operation in STOP Mode CPU Clock and WDT Operation Clock High Speed System Clock Watchdog timer Operating Operation stopped Operating fR fXP CPU operation Normal operation STOP Oscillation...

Page 180: ...on time set by the oscillation stabilization time select register OSTS has elapsed Watchdog timer Operating Operation stopped Operating fR fXP CPU operation 17 clocks Normal operation Ring OSC clock C...

Page 181: ...l operation Ring OSC clock Oscillation stopped STOP Oscillation stabilization time set by OSTS register Operating Operation stopped 9 4 4 Watchdog timer operation in HALT mode when Ring OSC can be sto...

Page 182: ...ction function This function is to detect a voltage drop in a battery The values of the A D conversion result ADCR register value and power fail comparison threshold register PFT are compared INTAD is...

Page 183: ...hold circuit samples the input signal of the analog input pin selected by the selector when A D conversion is started and holds the sampled analog input voltage value during A D conversion 3 Series re...

Page 184: ...verter is not used The signal input to ANI0 to ANI3 is converted into a digital signal based on the voltage applied across AVREF and AVSS In the standby mode the current flowing through the series res...

Page 185: ...ctionNote 1 288 fX 240 fX 192 fX 144 fX 120 fX 96 fX Setting prohibited FR2 0 0 0 1 1 1 Other than above FR1 0 0 1 0 0 1 FR0 0 1 0 0 1 0 0 1 2 3 4 5 6 7 ADM Address FF28H After reset 00H R W Symbol 34...

Page 186: ...tor Is Used ADCE Boost reference voltage ADCS Conversion operation Conversion operation Conversion stopped Conversion waiting Boost reference voltage generator operating Note Note The time from the ri...

Page 187: ...The lower six bits are fixed to 0 Each time A D conversion ends the conversion result is loaded from the successive approximation register and is stored in ADCR in order starting from the most signifi...

Page 188: ...No INTAD generation Higher 8 bits of ADCR PFT Higher 8 bits of ADCR PFT Higher 8 bits of ADCR PFT Higher 8 bits of ADCR PFT PFCM 0 1 0 1 2 3 4 5 6 7 PFM Address FF2AH After reset 00H R W Symbol Cauti...

Page 189: ...e analog input is greater than 1 2 AVREF the MSB of SAR remains set to 1 If the analog input is smaller than 1 2 AVREF the MSB is reset to 0 8 Next bit 8 of SAR is automatically set to 1 and the opera...

Page 190: ...performed continuously until bit 7 ADCS of the A D converter mode register ADM is reset 0 by software If any of ADM the analog input channel specification register ADS power fail comparison mode regi...

Page 191: ...ich returns integer part of value in parentheses VAIN Analog input voltage AVREF AVREF pin voltage ADCR A D conversion result register ADCR value SAR Successive approximation register Figure 10 10 sho...

Page 192: ...hen A D conversion has been completed the result of the A D conversion is stored in the A D conversion result register ADCR and an interrupt request signal INTAD is generated Once the next A D convers...

Page 193: ...PFT and an interrupt request signal INTAD is generated under the condition specified by bit 6 PFCM of PFM 1 When PFEN 1 and PFCM 0 The higher 8 bits of ADCR and PFT values are compared when A D conve...

Page 194: ...tion 1 Set bit 7 PFEN of the power fail comparison mode register PFM to 1 2 Set power fail comparison condition using bit 6 PFCM of PFM 3 Set bit 0 ADCE of the A D converter mode register ADM to 1 4 S...

Page 195: ...heoretical value Zero scale error full scale error integral linearity error and differential linearity errors that are combinations of these express the overall error Note that the quantization error...

Page 196: ...egree to which the conversion characteristics deviate from the ideal linear relationship It expresses the maximum value of the difference between the actual measurement value and the ideal straight li...

Page 197: ...e 10 2 2 Input range of ANI0 to ANI3 Observe the rated range of the ANI0 to ANI3 input voltage If a voltage of AVREF or higher and AVSS or lower even in the range of absolute maximum ratings is input...

Page 198: ...is applied to the pins adjacent to the pins currently being used for A D conversion the expected value of the A D conversion may not be obtained due to coupling noise Therefore do not apply a pulse t...

Page 199: ...ANIm ANIm A D conversion ADCR ADIF ADS rewrite start of ANIn conversion ADS rewrite start of ANIm conversion ADIF is set but ANIm conversion has not finished Remarks 1 n 0 to 3 2 m 0 to 3 9 Conversio...

Page 200: ...rsion Start Delay ADCS Wait period Conversion time Conversion time A D conversion start delay time Sampling time Sampling timing INTAD ADCS 1 or ADS rewrite Sampling time Table 10 3 A D Converter Samp...

Page 201: ...below Figure 10 22 Internal Equivalent Circuit of ANIn Pin ANIn C1 C2 C3 R1 R2 Table 10 4 Resistance and Capacitance Values of Equivalent Circuit Reference Values AVREF R1 R2 C1 C2 C3 2 7 V 12 k 8 k...

Page 202: ...rmed independently Four operating clock inputs selectable Fixed to LSB first communication Cautions 1 If clock supply to serial interface UART0 is not stopped e g in the HALT mode normal operation con...

Page 203: ...ble 11 1 Configuration of Serial Interface UART0 Item Configuration Registers Receive buffer register 0 RXB0 Receive shift register 0 RXS0 Transmit shift register 0 TXS0 Control registers Asynchronous...

Page 204: ...Receive shift register 0 RXS0 Receive buffer register 0 RXB0 Asynchronous serial interface reception error status register 0 ASIS0 Asynchronous serial interface operation mode register 0 ASIM0 Baud ra...

Page 205: ...n be read by an 8 bit memory manipulation instruction No data can be written to this register RESET input or POWER0 0 sets this register to FFH 2 Receive shift register 0 RXS0 This register converts t...

Page 206: ...01H Figure 11 2 Format of Asynchronous Serial Interface Operation Mode Register 0 ASIM0 1 2 Address FF70H After reset 01H R W Symbol 7 6 5 4 3 2 1 0 ASIM0 POWER0 TXE0 RXE0 PS01 PS00 CL0 SL0 1 POWER0 E...

Page 207: ...errupt does not occur Cautions 1 At startup set POWER0 to 1 and then set TXE0 to 1 To stop the operation clear TXE0 to 0 and then clear POWER0 to 0 2 At startup set POWER0 to 1 and then set RXE0 to 1...

Page 208: ...register is read 1 If the parity of transmit data does not match the parity bit on completion of reception FE0 Status flag indicating framing error 0 If POWER0 0 and RXE0 0 or if the ASIS0 register is...

Page 209: ...5 MHz 1 1 fX 2 5 312 5 kHz MDL04 MDL03 MDL02 MDL01 MDL00 k Selection of 5 bit counter output clock 0 0 Setting prohibited 0 1 0 0 0 8 fXCLK0 8 0 1 0 0 1 9 fXCLK0 9 0 1 0 1 0 10 fXCLK0 10 1 1 0 1 0 26...

Page 210: ...ystem clock oscillation frequency 3 k Value set by the MDL04 to MDL00 bits k 8 9 10 31 4 Don t care 5 Figures in parentheses apply to operation at fX 10 MHz 4 Port mode register 1 PM1 This register se...

Page 211: ...1H R W Symbol 7 6 5 4 3 2 1 0 ASIM0 POWER0 TXE0 RXE0 PS01 PS00 CL0 SL0 1 POWER0 Enables disables operation of internal operation clock 0 Note 1 Disables operation of the internal operation clock fixes...

Page 212: ...egister see Figure 11 2 3 Set bit 7 POWER0 of the ASIM0 register to 1 4 Set bit 6 TXE0 of the ASIM0 register to 1 Transmission is enabled Set bit 5 RXE0 of the ASIM0 register to 1 Reception is enabled...

Page 213: ...s 7 or 8 bits LSB first Parity bit Even parity odd parity 0 parity or no parity Stop bit 1 or 2 bits The character bit length parity and stop bit length in one data frame are specified by asynchronous...

Page 214: ...at are 1 in the receive data including the parity bit is counted If it is odd a parity error occurs ii Odd parity Transmission Unlike even parity transmit data including the parity bit is controlled s...

Page 215: ...data in order starting from the LSB When transmission is completed the parity and stop bits set by ASIM0 are appended and a transmission completion interrupt request INTST0 is generated Transmission i...

Page 216: ...ud rate When the stop bit has been received the reception completion interrupt INTSR0 is generated and the data of RXS0 is written to receive buffer register 0 RXB0 If an overrun error OVE0 occurs how...

Page 217: ...Table 11 3 Cause of Reception Error Reception Error Cause Parity error The parity specified for transmission does not match the parity of the receive data Framing error Stop bit is not detected Overru...

Page 218: ...ops cleared to 0 when bit 7 POWER0 or bit 6 TXE0 of asynchronous serial interface operation mode register 0 ASIM0 is 0 It starts counting when POWER0 1 and TXE0 1 The counter is cleared to 0 when the...

Page 219: ...S00 bits of the BRGC0 register k Value set by the MDL04 to MDL00 bits of the BRGC0 register k 8 9 10 31 b Error of baud rate The baud rate error can be calculated by the following expression Error 1 1...

Page 220: ...99 1 03 10400 3 15 10417 0 16 3 13 10072 3 15 2 25 10475 0 72 19200 3 8 19531 1 73 2 27 19398 1 03 2 14 18705 2 58 31250 2 20 31250 0 2 17 30809 1 41 38400 2 16 39063 1 73 2 14 38796 2 58 2 27 38796 1...

Page 221: ...gth of UART0 Start bit Bit 0 Bit 1 Bit 7 Parity bit Minimum permissible data frame length Maximum permissible data frame length Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Latch timing Stop bit St...

Page 222: ...Brate The permissible baud rate error between UART0 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions as follows Table 11 5 Maximum Minimum P...

Page 223: ...field transmission from 13 to 20 bits More than 11 bits can be identified for synchronous break field reception SBF reception flag provided Cautions 1 The TXD6 output inversion function inverts only...

Page 224: ...fore communication is possible when the baud rate error in the slave is 15 or less Figures 12 1 and 12 2 outline the transmission and reception operations of LIN Figure 12 1 LIN Transmission Operation...

Page 225: ...ut This SBF reception completion interrupt enables the capture timer Detection of errors OVE6 PE6 and FE6 is suppressed and error detection processing of UART communication and data transfer of the sh...

Page 226: ...tor Selector Selector Selector Port mode PM00 Output latch P00 Remark ISC0 ISC1 Bits 0 and 1 of the input switch control register ISC see Figure 12 11 The peripheral functions used in the LIN communic...

Page 227: ...gister 6 RXS6 Transmit buffer register 6 TXB6 Transmit shift register 6 TXS6 Control registers Asynchronous serial interface operation mode register 6 ASIM6 Asynchronous serial interface reception err...

Page 228: ...r register 6 RXB6 RXD6 P14 TI000 INTP0Note INTSR6 Baud rate generator Filter INTSRE6 Asynchronous serial interface reception error status register 6 ASIS6 Asynchronous serial interface operation mode...

Page 229: ...XS6 cannot be directly manipulated by a program 3 Transmit buffer register 6 TXB6 This buffer register is used to set transmit data Transmission is started when data is written to TXB6 This register c...

Page 230: ...ion when bit 7 POWER6 and bit 6 TXE6 of ASIM6 1 or bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 Figure 12 5 Format of Asynchronous Serial Interface Operation Mode Register 6 ASIM6 1 2 Address FF50H After re...

Page 231: ...R6 does not occur 1 INTSR6 occurs in case of error at this time INTSRE6 does not occur Note If reception as 0 parity is selected the parity is not judged Therefore bit 2 PE6 of asynchronous serial int...

Page 232: ...s read 1 If the parity of transmit data does not match the parity bit on completion of reception FE6 Status flag indicating framing error 0 If POWER6 0 and RXE6 0 or if ASIS6 register is read 1 If the...

Page 233: ...6 0 or TXE6 0 or if data is transferred to transmit shift register 6 TXS6 1 If data is written to transmit buffer register 6 TXB6 if data exists in TXB6 TXSF6 Transmit shift register data flag 0 If PO...

Page 234: ...0 1 1 fX 2 3 1 25 MHz 0 1 0 0 fX 2 4 625 kHz 0 1 0 1 fX 2 5 312 5 kHz 0 1 1 0 fX 2 6 156 25 kHz 0 1 1 1 fX 2 7 78 13 kHz 1 0 0 0 fX 2 8 39 06 kHz 1 0 0 1 fX 2 9 19 53 kHz 1 0 1 0 fX 2 10 9 77 kHz 1 0...

Page 235: ...ator is divided and supplied as the count clock If the base clock is the Ring OSC clock the operation of serial interface UART6 is not guaranteed 2 Make sure POWER6 0 when rewriting TPS63 to TPS60 Rem...

Page 236: ...7H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of 8 bit counter 0 0 0 0 0...

Page 237: ...WER6 and bit 5 RXE6 of ASIM6 1 Note however that communication is started by the refresh operation because bit 6 SBRT6 of ASICL6 is cleared to 0 when communication is completed when an interrupt signa...

Page 238: ...al output of TXD6 1 Inverted output of TXD6 Cautions 1 In the case of an SBF reception error return the mode to the SBF reception mode and hold the status of the SBRF6 flag 2 Before setting the SBRT6...

Page 239: ...source selection 0 TI000 P00 1 RxD6 P14 ISC0 INTP0 input source selection 0 INTP0 P120 1 RxD6 P14 8 Port mode register 1 PM1 This register sets port 1 input output in 1 bit units When using the P13 T...

Page 240: ...disables operation of internal operation clock 0 Note 1 Disables operation of the internal operation clock fixes the clock to low level and asynchronously resets the internal circuit Note 2 TXE6 Enabl...

Page 241: ...ntrol register 6 BRGC6 Asynchronous serial interface control register 6 ASICL6 Input switch control register ISC Port mode register 1 PM1 Port register 1 P1 The basic procedure of setting an operation...

Page 242: ...6 RXE6 PM13 P13 PM14 P14 UART6 Operation TxD6 P13 RxD6 P14 0 0 0 Note Note Note Note Stop P13 P14 0 1 Note Note 1 Reception P13 RxD6 1 0 0 1 Note Note Transmission TxD6 P14 1 1 1 0 1 1 Transmission re...

Page 243: ...ansmission reception Start bit Parity bit D7 D6 D5 D4 D3 1 data frame Character bits D2 D1 D0 Stop bit One data frame consists of the following bits Start bit 1 bit Character bits 7 or 8 bits Parity b...

Page 244: ...y Stop bit 1 bit Communication data 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3 Data length 8 bits MSB first Parity Even parity Stop bit 1 bit Communication data 55H TXD6 pin inverted...

Page 245: ...ion The number of bits that are 1 in the receive data including the parity bit is counted If it is odd a parity error occurs ii Odd parity Transmission Unlike even parity transmit data including the p...

Page 246: ...ansferred to transmit shift register 6 TXS6 After that the data is sequentially output from TXS6 to the TXD6 pin When transmission is completed the parity bit and stop bit set by ASIM6 are added and a...

Page 247: ...ncorporated in a LIN the continuous transmission function cannot be used Make sure that asynchronous serial interface transmission status register 6 ASIF6 is 00H before writing transmit data to transm...

Page 248: ...6 Transfer executed necessary number of times Yes Read ASIF6 TXBF6 0 No No Yes Transmission completion interrupt occurs Read ASIF6 TXSF6 0 No No No Yes Yes Yes Yes Completion of transmission processin...

Page 249: ...1 Data 1 Data 2 Data 3 Data 2 Data 1 Data 3 FF FF Parity Stop Data 2 Parity Stop TXB6 TXS6 TXBF6 TXSF6 Start Start Note Note When ASIF6 is read there is a period in which TXBF6 and TXSF6 1 1 Therefore...

Page 250: ...op TXB6 TXS6 TXBF6 TXSF6 POWER6 or TXE6 Start Remark TXD6 TXD6 pin output INTST6 Interrupt request signal TXB6 Transmit buffer register 6 TXS6 Transmit shift register 6 ASIF6 Asynchronous serial inter...

Page 251: ...the stop bit has been received the reception completion interrupt INTSR6 is generated and the data of RXS6 is written to receive buffer register 6 RXB6 If an overrun error OVE6 occurs however the rece...

Page 252: ...Reception Error Cause Parity error The parity specified for transmission does not match the parity of the receive data Framing error Stop bit is not detected Overrun error Reception of the next data i...

Page 253: ...ecessary use the baud rate value of the normal UART transmission function Setting method Transmit 00H by setting the number of character bits of the data to 8 bits and the parity bit to 0 parity or ev...

Page 254: ...6 register Set TXE6 bit of ASIM6 register to 1 to enable transmission Set TXB6 register to 00H and start transmission after SBTT6 bit is set to 1 INTST6 occurred No Yes Clear TXE6 and RXE6 bits of ASI...

Page 255: ...quest INTSR6 is generated as normal processing At this time the SBRF6 and SBRT6 bits are automatically cleared and SBF reception ends Detection of errors such as OVE6 PE6 and FE6 bits 0 to 2 of asynch...

Page 256: ...level when POWER6 0 Transmission counter This counter stops cleared to 0 when bit 7 POWER6 or bit 6 TXE6 of asynchronous serial interface operation mode register 6 ASIM6 is 0 It starts counting when...

Page 257: ...ate generator BRGC6 MDL67 to MDL60 1 2 POWER6 TXE6 or RXE6 CKSR6 TPS63 to TPS60 fX fX 2 fX 22 fX 23 fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 fX 210 8 bit timer event counter 50 output fXCLK6 Remark POWER6...

Page 258: ...to TPS60 bits of CKSR6 register k Value set by MDL67 to MDL60 bits of BRGC6 register k 8 9 10 255 b Error of baud rate The baud rate error can be calculated by the following expression Error 1 100 Cau...

Page 259: ...610 0 11 1H 109 9610 0 11 10400 2H 120 10417 0 16 2H 101 10371 0 28 1H 101 10475 0 28 19200 1H 130 19231 0 16 1H 109 19200 0 11 0H 109 19220 0 11 31250 1H 80 31250 0 00 0H 134 31268 0 06 0H 67 31268 0...

Page 260: ...Minimum permissible data frame length Maximum permissible data frame length Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Latch timing Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As sh...

Page 261: ...between UART6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions as follows Table 12 5 Maximum Minimum Permissible Baud Rate Error Division Rat...

Page 262: ...cted because the timing is initialized on the reception side when the start bit is detected Figure 12 27 Data Frame Length During Continuous Transmission Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bi...

Page 263: ...I O mode because transmission and reception can be simultaneously executed In addition whether 8 bit data is communicated with the MSB or LSB first can be specified so this interface can be connected...

Page 264: ...al operation mode register 10 CSIM10 are 1 The data written to SOTB10 is converted from parallel data into serial data by serial I O shift register 10 and output to the serial output pin SO10 SOTB10 c...

Page 265: ...in 3 wire serial I O mode 0 Disables operation Note 2 and asynchronously resets the internal circuit Note 3 1 Enables operation TRMD10 Note 4 Transmit receive mode control 0 Note 5 Receive mode transm...

Page 266: ...ransmission reception timing Type 0 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 inpu...

Page 267: ...Port mode register 1 PM1 This register sets port 1 input output in 1 bit units When using P10 SCK10 TxD0Note as the clock output pins of the serial interface and P12 SO10 as the data output pins clear...

Page 268: ...by serial operation mode register 10 CSIM10 To set the operation stop mode clear bit 7 CSIE10 of CSIM10 to 0 a Serial operation mode register 10 CSIM10 CSIM10 can be set by a 1 bit or 8 bit memory ma...

Page 269: ...ion register 10 CSIC10 Port mode register 1 PM1 Port register 1 P1 The basic procedure of setting an operation in the 3 wire serial I O mode is as follows 1 Set the CSIC10 register see Figure 13 3 2 S...

Page 270: ...0 Note 4 SO10 SCK10 input Note 3 1 1 1 0 0 1 Slave transmission reception Note 3 SI10 SO10 SCK10 input Note 3 1 0 1 Note 1 Note 1 0 1 Master reception SI10 P12 SCK10 output 1 1 Note 1 Note 1 0 0 0 1 M...

Page 271: ...egister 10 CSIM10 is 0 Reception is started when data is read from serial I O shift register 10 SIO10 After communication has been started bit 0 CSOT10 of CSIM10 is set to 1 When communication of 8 bi...

Page 272: ...gure 13 5 Timing in 3 Wire Serial I O Mode 2 2 2 Transmission reception timing Type 2 TRMD10 1 DIR10 0 CKP10 0 DAP10 1 ABH 56H ADH 5AH B5H 6AH D5H SCK10 SOTB10 SIO10 CSOT10 CSIIF10 SO10 SI10 input AAH...

Page 273: ...10 SI10 capture CSIIF10 CSOT10 b Type 2 CKP10 0 DAP10 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 Writing to SOTB10 or reading from SIO10 SI10 capture CSIIF10 CSOT10 c Type 3 CKP10 1 DAP10 0 D7 D6 D5 D4 D3 D...

Page 274: ...it of the receive data is stored in the SIO10 register via the SI10 pin The second and subsequent bits are latched by the SIO10 register to the output latch at the next falling or rising edge of SCK10...

Page 275: ...e of the last bit Figure 13 8 Output Value of SO10 Pin Last Bit 1 Type 1 when CKP10 0 and DAP10 0 or CKP10 1 DAP10 0 SCK10 SOTB10 SIO10 SO10 Writing to SOTB10 or reading from SIO10 Next request is iss...

Page 276: ...tatus TRMD10 DAP10 DIR10 SO10 Output Note 1 TRMD10 0 Note 2 Outputs low level Note 2 DAP10 0 Value of SO10 latch low level output DIR10 0 Value of bit 7 of SOTB10 TRMD10 1 DAP10 1 DIR10 1 Value of bit...

Page 277: ...priority are simultaneously generated each interrupt is serviced according to its predetermined priority see Table 14 1 A standby release signal is generated and the STOP mode and HALT mode are releas...

Page 278: ...ed 001CH 13 INTTM50 Match between TM50 and CR50 when compare register is specified 001EH 14 INTTM000 Match between TM00 and CR000 when compare register is specified 0020H 15 INTTM010 Match between TM0...

Page 279: ...signal B External maskable interrupt INTP0 to INTP5 Internal bus Interrupt request IF MK IE PR ISP Priority controller Vector table address generator Standby release signal External interrupt edge en...

Page 280: ...upt Request Register Register Register INTLVI LVIIF IF0L LVIMK MK0L LVIPR PR0L INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2 PMK2 PPR2 INTP3 PIF3 PMK3 PPR3 INTP4 PIF4 PMK4 PPR4 INTP5 PIF5 PMK5...

Page 281: ...FFE0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0L SREIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF Address FFE1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0H TMIF010 TMIF000 TMIF50 TMIFH0 TMIFH1 DUA...

Page 282: ...sets these registers to FFH Figure 14 3 Format of Interrupt Mask Flag Register MK0L MK0H MK1L Address FFE4H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0L SREMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK...

Page 283: ...on RESET input sets these registers to FFH Figure 14 4 Format of Priority Specification Flag Register PR0L PR0H PR1L Address FFE8H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0L SREPR6 PPR5 PPR4 PPR3...

Page 284: ...EGP5 EGP4 EGP3 EGP2 EGP1 EGP0 Address FF49H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGN 0 0 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0 EGPn EGNn INTPn pin valid edge selection n 0 to 5 0 0 Edge detection disabl...

Page 285: ...y saved into a stack and the IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specification flag of the acknowledged interrupt are transferred to the...

Page 286: ...Time Note When PR 0 7 clocks 32 clocks When PR 1 8 clocks 33 clocks Note If an interrupt request is generated just before a divide instruction the wait time becomes longer Remark 1 clock 1 fCPU fCPU...

Page 287: ...est held pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Vectored interrupt servicing Any high priority interrupt re...

Page 288: ...errupt servicing program CPU processing IF PR 1 IF PR 0 6 clocks 25 clocks Remark 1 clock 1 fCPU fCPU CPU clock 14 4 2 Software interrupt request acknowledgment A software interrupt request is acknowl...

Page 289: ...currently being serviced is generated during interrupt servicing it is not acknowledged for multiple interrupt servicing Interrupt requests that are not enabled because interrupts are in the interrup...

Page 290: ...nowledged the EI instruction must always be issued to enable interrupt request acknowledgment Example 2 Multiple interrupt servicing does not occur due to priority control Main processing INTxx servic...

Page 291: ...EI 1 instruction execution RETI RETI INTxx PR 0 INTyy PR 0 IE 0 IE 0 IE 1 IE 1 Interrupts are not enabled during servicing of interrupt INTxx EI instruction is not issued therefore interrupt request I...

Page 292: ...0L IF0H IF1L MK0L MK0H MK1L PR0L PR0H and PR1L registers Caution The BRK instruction is not one of the above listed interrupt request hold instructions However the software interrupt activated by exec...

Page 293: ...ing Oscillating Stopped Note 4 Ring OSC High speed system clock Notes 1 When Cannot be stopped is selected for Ring OSC by the option byte 2 When Can be stopped by software is selected for Ring OSC by...

Page 294: ...rried out However because a wait time is required to secure the oscillation stabilization time after the STOP mode is released select the HALT mode if it is necessary to start processing immediately u...

Page 295: ...on Time Counter Status Register OSTC Address FFA3H After reset 00H R Symbol 7 6 5 4 3 2 1 0 OSTC 0 0 0 MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status MOST11 MOST13 MOST14 MOS...

Page 296: ...MHz fXP 16 MHz 0 0 1 2 11 fXP 204 8 s 128 s 0 1 0 2 13 fXP 819 2 s 512 s 0 1 1 2 14 fXP 1 64 ms 1 02 ms 1 0 0 2 15 fXP 3 27 ms 2 04 ms 1 0 1 2 16 fXP 6 55 ms 4 09 ms Other than above Setting prohibit...

Page 297: ...teed when count clock other than TI50 is selected 8 bit timer H0 Operable Operation not guaranteed when count clock other than TM50 output is selected during 8 bit timer event counter 50 operation 8 b...

Page 298: ...t is disabled the next address instruction is executed Figure 15 3 HALT Mode Release by Interrupt Request Generation HALT instruction Wait Wait Operating mode HALT mode Operating mode Oscillation High...

Page 299: ...ime is not required when the external RC oscillation clock is selected as the high speed system clock by the option byte Therefore the CPU clock can be switched without reading the OSTC value 2 When R...

Page 300: ...k Only high speed system clock oscillator oscillation is stopped Clock supply to the CPU is stopped CPU Operation stopped Port output latch Holds the status before STOP mode was set 16 bit timer event...

Page 301: ...cted as CPU clock when STOP instruction is executed Ring OSC clock High speed system clock High speed system clock is selected as CPU clock when STOP instruction is executed STOP mode release STOP mod...

Page 302: ...igh speed system clock is used as CPU clock Operating mode Operating mode Oscillates Oscillates STOP instruction STOP mode Wait set by OSTS Standby release signal Oscillation stabilization wait status...

Page 303: ...not required when the external RC oscillation clock is selected as the high speed system clock by the option byte Therefore the CPU clock can be switched without reading the OSTC value 2 When Ring OSC...

Page 304: ...reset input or during the oscillation stabilization time just after reset release except for P130 which is low level output When a high level is input to the RESET pin the reset is released and progr...

Page 305: ...og timer reset signal Clock monitor reset signal RESET Power on clear circuit reset signal Low voltage detector reset signal Reset signal Reset signal Reset signal to LVIM LVIS register Clear Set Set...

Page 306: ...effected the output signal of P130 can be dummy output as the reset signal to the CPU Figure 16 3 Timing of Reset Due to Watchdog Timer Overflow Hi Z Normal operation Reset period Oscillation stop CPU...

Page 307: ...17 fR Normal operation Reset processing Ring OSC clock High speed system clock Ring OSC clock Port pin P130 Note Note Set P130 to high level output by software Remarks 1 When reset is effected P130 ou...

Page 308: ...ounter 00 TM00 0000H Capture compare registers 000 010 CR000 CR010 0000H Mode control register 00 TMC00 00H Prescaler mode register 00 PRM00 00H Capture compare control register 00 CRC00 00H 16 bit ti...

Page 309: ...10 SIO10 00H Serial operation mode register 10 CSIM10 00H Serial interface CSI10 Serial clock selection register 10 CSIC10 00H Clock monitor Mode register CLM 00H Reset function Reset control flag reg...

Page 310: ...nal reset request is not generated or RESF is cleared 1 Internal reset request is generated CLMRF Internal reset request by clock monitor CLM 0 Internal reset request is not generated or RESF is clear...

Page 311: ...k is stopped by software MSTOP 1 or MCC 1 and during the oscillation stabilization time When the Ring OSC clock is stopped Remark MSTOP Bit 7 of the main OSC control register MOC 17 2 Configuration of...

Page 312: ...RESET input clears this register to 00H Figure 17 2 Format of Clock Monitor Mode Register CLM 7 0 CLME 0 1 Symbol CLM Address FFA9H After reset 00H R W 6 0 Disables clock monitor operation Enables clo...

Page 313: ...stopped Remark MSTOP Bit 7 of the main OSC control register MOC Table 17 2 Operation Status of Clock Monitor When CLME 1 CPU Operation Clock Operation Mode High Speed System Clock Status Ring OSC Clo...

Page 314: ...tabilization time Oscillation stopped 17 clocks Set to 1 by software RESET RESET input clears bit 0 CLME of the clock monitor mode register CLM to 0 and stops the clock monitor operation Even if CLME...

Page 315: ...n stabilization time is not required when the external RC oscillation clock is selected as the high speed system clock by the option byte Therefore the CPU clock can be switched without reading the OS...

Page 316: ...at the end of the high speed system clock oscillation stabilization time Monitoring is stopped in STOP mode and during the oscillation stabilization time 6 Clock monitor status after high speed syste...

Page 317: ...ng Monitoring stopped Monitoring CLME When bit 0 CLME of the clock monitor mode register CLM is set to 1 before or while oscillation of the Ring OSC clock is stopped monitoring automatically starts af...

Page 318: ...he supply voltage is VDD 2 0 to 5 5 V when the Ring OSC clock or subsystem clock is used but be sure to use the product in a voltage range of 2 2 to 5 5 V because the detection voltage VPOC of the POC...

Page 319: ...wer on Clear Circuit Detection voltage source VPOC Internal reset signal VDD VDD 18 3 Operation of Power on Clear Circuit In the power on clear circuit the supply voltage VDD and detection voltage VPO...

Page 320: ...en the reset signal is generated The cause of reset power on clear WDT LVI or clock monitor can be identified by the RESF register Change the CPU clock from the Ring OSC clock to the high speed system...

Page 321: ...sing After Release of Reset 2 2 Checking reset cause Yes No Check reset cause Power on clear external reset generated Reset processing by watchdog timer Reset processing by clock monitor Reset process...

Page 322: ...y software Operable in STOP mode When the low voltage detector is used to reset bit 0 LVIRF of the reset control flag register RESF is set to 1 if reset occurs For details of RESF see CHAPTER 16 RESET...

Page 323: ...terrupt signal when supply voltage VDD detection voltage VLVI 1 Generates internal reset signal when supply voltage VDD detection voltage VLVI LVIF Note 5 Low voltage detection flag 0 Supply voltage V...

Page 324: ...IS1 2 LVIS2 3 LVIS3 4 0 5 0 6 0 7 0 Symbol LVIS Address FFBFH After reset 00H R W LVIS3 LVIS2 LVIS1 LVIS0 Detection level Note 0 0 0 0 VLVI0 4 3 V 0 2 V 0 0 0 1 VLVI1 4 1 V 0 2 V 0 0 1 0 VLVI2 3 9 V 0...

Page 325: ...nables LVI operation 4 Use software to instigate a wait of at least 0 2 ms 5 Wait until it is checked that supply voltage VDD detection voltage VLVI by bit 0 LVIF of LVIM 6 Set bit 1 LVIMD of LVIM to...

Page 326: ...rnal reset signal Cleared by software Not cleared Not cleared Not cleared Not cleared Cleared by software 5 6 Clear Clear Clear 4 0 2 ms or longer LVION flag set by software LVIMD flag set by software...

Page 327: ...is checked that supply voltage VDD detection voltage VLVI by bit 0 LVIF of LVIM 6 Clear the interrupt request flag of LVI LVIIF to 0 7 Release the interrupt mask flag of LVI LVIMK 8 Execute the EI ins...

Page 328: ...e 2 7 Cleared by software LVIMK flag set by software LVIF flag INTLVI LVIIF flag Internal reset signal 3 5 6 Cleared by software 4 0 2 ms or longer LVION flag set by software Note 2 Note 2 1 Note 1 No...

Page 329: ...tem may be repeatedly reset and released from the reset status In this case the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action...

Page 330: ...OSTC registerNote 3 TMIFH1 1 Interrupt request is generated Initialization of ports 8 bit timer H1 can operate with the Ring OSC clock Source fR 480 kHz MAX 27 compare value 200 53 ms fR Ring OSC clo...

Page 331: ...ESF register 1 LVIRF of RESF register 1 Yes No 2 When used as interrupt Check that supply voltage VDD detection voltage VLVI in the servicing routine of the LVI interrupt by using bit 0 LVIF of the lo...

Page 332: ...ion Byte Address 0080H 7 6 5 4 3 2 1 0 OSCSEL0 RINGOSC OSCSEL0 High speed system clock oscillation selection 0 Crystal ceramic oscillation 1 External RC oscillation RINGOSC Ring OSC oscillation 0 Can...

Page 333: ...ytes PD78F0103 768 bytes Note PD780101 512 bytes PD780102 768 bytes PD780103 768 bytes Pin 5 FLMD0 pin VPP pin IC pin Pin 22 P17 TI50 TO50 FLMD1 pin P17 TI50 TO50 pin Power on clear POC circuit Detect...

Page 334: ...1 2 Figure 21 1 Format of Internal Memory Size Switching Register IMS Address FFF0H After reset CFH R W Symbol 7 6 5 4 3 2 1 0 IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0 Internal high spe...

Page 335: ...CSI10 With CSI10 HS With UART6 Signal Name I O Pin Function Pin Name Pin No Pin Name Pin No Pin Name Pin No SI RxD Input Receive signal SO10 P12 17 SO10 P12 17 TxD6 P13 18 SO TxD Output Transmit signa...

Page 336: ...he adapter for flash memory writing are shown below Figure 21 2 Example of Wiring Adapter for Flash Memory Writing in 3 Wire Serial I O CSI10 Mode 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6...

Page 337: ...igure 21 3 Example of Wiring Adapter for Flash Memory Writing in 3 Wire Serial I O CSI10 HS Mode 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 LVDD VDD GND SI SO SCK...

Page 338: ...UD 338 Figure 21 4 Example of Wiring Adapter for Flash Memory Writing in UART UART6 Mode 28 27 26 30 29 25 24 23 22 21 20 19 18 16 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 LVDD VDD GND SI SO SCK CLK RES...

Page 339: ...erface between the dedicated flash programmer and the 78K0 KB1 CSI10 or UART6 is used for manipulation such as writing and erasing To write the flash memory off board a dedicated program adapter FA se...

Page 340: ...D SO TxD SCK X1 CL1 CLK X2 CL2 H S Dedicated flash programmer PG FP4 Flash Pro4 Cxxxxxx Bxxxxx Axxxx XXX YYY XXXXX XXXXXX XXXX XXXX YYYY STATVE VDD AVREF VSS AVSS 3 UART6 Transfer rate 4800 to 76800 b...

Page 341: ...FLMD1 VDD I O VDD voltage generation VDD AVREF GND Ground VSS AVSS CLK Output Clock output to 78K0 KB1 X1 CL1 X2 CL2 Note RESET Output Reset signal RESET SI RxD Input Receive signal SO10 TxD6 SO TxD O...

Page 342: ...ed as described below 21 5 1 FLMD0 pin In the normal operation mode 0 V is input to the FLMD0 pin In the flash memory programming mode the VDD write voltage is supplied to the FLMD0 pin An FLMD0 pin c...

Page 343: ...1 5 Pins Used by Each Serial Interface Serial Interface Pins Used CSI10 SO10 SI10 SCK10 CSI10 HS SO10 SI10 SCK10 HS P15 UART6 TxD6 RxD6 To connect the dedicated flash programmer to the pins of a seria...

Page 344: ...efore isolate the signal of the other device 78K0 KB1 2 Malfunction of other device If the dedicated flash programmer output or input is connected to a pin input or output of a serial interface connec...

Page 345: ...cated flash programmer Therefore isolate the signal of the reset signal generator 78K0 KB1 21 5 5 Port pins When the flash memory programming mode is set all the pins not used for flash memory program...

Page 346: ...D0 pulse supply No End Flash memory programming mode is set 21 6 2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash programmer set the 78K0 KB1 in...

Page 347: ...munication Mode Port Speed On Target Frequency Multiply Rate Pins Used Number of FLMD0 Pulses UART UART6 UART ch0 4800 to 76800 bps Notes 2 3 TxD6 RxD6 0 3 wire serial I O CSI10 SIO ch0 200 kHz to 2 M...

Page 348: ...d Erases the contents of the entire memory Blank check Batch blank check command Checks the erasure status of the entire memory High speed write command Writes data by specifying the write address and...

Page 349: ...of self programming is illustrated below Remark For details of the self programming function refer to a separate document to be published document name 78K0 Kx1 Application Note release schedule Pendi...

Page 350: ...r FLPMC This register is used to enable or disable writing or erasing of the flash memory and to set the operation mode during self programming The FLPMC can be written only in a specific sequence see...

Page 351: ...0 1 Notes 1 Differs depending on the operation mode User mode 08H On board mode 0CH 2 Bit 2 FWEPR is read only 3 For actual writing erasing the FLMD0 pin must be high FWEPR 1 as well as FWEDIS 0 FWED...

Page 352: ...ter cannot be written illegally Occurrence of an illegal store operation can be checked by bit 0 FPRERR of the flash status register PFS A5H must be written to PFCMD each time the value of FLPMC is ch...

Page 353: ...ted value of the value to be set to FLPMC is written by the first store instruction after 2 If the first store instruction operation after 3 is on a peripheral register other than FLPMC If a value oth...

Page 354: ...time Consequently the above area to be swapped is used as a boot area and the program is executed correctly Figure 21 21 shows an image of the boot swap function Note The boot flag is controlled by th...

Page 355: ...cluster 0 and boot cluster 1 in the figure are exchanged Figure 21 22 Memory Map and Boot Area 1 3 1 PD78F0101H FF00H FEFFH FEE0H FEDFH FD00H FCFFH 2000H 1FFFH 1000H 0FFFH 1FFFH Boot cluster 0 4096 8...

Page 356: ...EE0H FEDFH FC00H FBFFH 4000H 3FFFH 1000H 0FFFH 2000H 1FFFH Boot cluster 0 4096 8 bits Boot cluster 1 4096 8 bits 8192 8 bits Special function registers SFR 256 8 bits General purpose registers 32 8 bi...

Page 357: ...EE0H FEDFH FC00H FBFFH 6000H 5FFFH 1000H 0FFFH 2000H 1FFFH Boot cluster 0 4096 8 bits Boot cluster 1 4096 8 bits 16384 8 bits Special function registers SFR 256 8 bits General purpose registers 32 8 b...

Page 358: ...hen using a label be sure to write the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can...

Page 359: ...ag AC Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register conten...

Page 360: ...HL B A 1 6 7 m HL B A A HL C 1 6 7 n A HL C MOV HL C A 1 6 7 m HL C A A r Note 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8 10 n m A addr16 A DE 1 4 6 n m A DE A HL 1 4 6 n m A HL A HL...

Page 361: ...8 9 n A CY A HL B ADD A HL C 2 8 9 n A CY A HL C A byte 2 4 A CY A byte CY saddr byte 3 6 8 saddr CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4 r CY r A CY A saddr 2 4 5 A CY A saddr CY A addr1...

Page 362: ...4 5 n A CY A HL CY A HL byte 2 8 9 n A CY A HL byte CY A HL B 2 8 9 n A CY A HL B CY SUBC A HL C 2 8 9 n A CY A HL C CY A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byte A r Note 3 2 4 A A r r A 2...

Page 363: ...HL A HL byte 2 8 9 n A A HL byte A HL B 2 8 9 n A A HL B XOR A HL C 2 8 9 n A A HL C A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2 4 5 A saddr A addr16 3 8 9...

Page 364: ...3 0 A3 0 HL 7 4 HL 3 0 ADJBA 2 4 Decimal Adjust Accumulator after Addition BCD adjustment ADJBS 2 4 Decimal Adjust Accumulator after Subtract CY saddr bit 3 6 7 CY saddr bit CY sfr bit 3 7 CY sfr bit...

Page 365: ...t saddr bit 2 4 6 saddr bit 1 sfr bit 3 8 sfr bit 1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1 SET1 HL bit 2 6 8 n m HL bit 1 saddr bit 2 4 6 saddr bit 0 sfr bit 3 8 sfr bit 0 A bit 2 4 A bit 0 PSW bit 2...

Page 366: ...2 SP 1 PSW SP SP 1 PUSH rp 1 4 SP 1 rpH SP 2 rpL SP SP 2 PSW 1 2 PSW SP SP SP 1 R R R POP rp 1 4 rpH SP 1 rpL SP SP SP 2 SP word 4 10 SP word SP AX 2 8 SP AX Stack manipulate MOVW AX SP 2 8 AX SP addr...

Page 367: ...disp8 if A bit 1 then reset A bit PSW bit addr16 4 12 PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit BTCLR HL bit addr16 3 10 12 n m PC PC 3 jdisp8 if HL bit 1 then reset HL bit B addr16 2 6 B B 1 the...

Page 368: ...16 1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD...

Page 369: ...rp MOVW MOVW addr16 MOVW SP MOVW MOVW Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand First Operand A bit sfr bit saddr bit PSW...

Page 370: ...h instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand First Operand AX addr16 addr11 addr5 addr16 Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ Compound instruct...

Page 371: ...30 mA Output current high IOH Total of pins 60 mA P00 to P03 P10 to P17 P130 30 mA Per pin 20 mA P30 to P33 P120 35 mA Output current low IOL Total of all pins 70 mA P00 to P03 P10 to P17 P130 35 mA I...

Page 372: ...wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring wi...

Page 373: ...ure to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line throug...

Page 374: ...DD 5 5 V 0 0 3AVREF V VIL3 P20 to P23 Note 2 2 0 V VDD 2 7 V 0 0 2AVREF V Input voltage low VIL4 X1 X2 2 7 V VDD 5 5 V 0 0 4 V Total of P30 to P33 P120 pins IOH 25 mA 4 0 V VDD 5 5 V IOH 5 mA VDD 1 0...

Page 375: ...converter is stopped 4 0 8 0 mA IDD3 RC oscillation operating mode Note 8 fXP 4 MHz VDD 3 0 V 10 When A D converter is operating Note 5 5 0 10 0 mA When peripheral functions are stopped 3 0 6 0 mA fXP...

Page 376: ...D 5 5 V 2 fsam 0 1 Note 2 s TI000 TI010 input high level width low level width tTIH0 tTIL0 2 7 V VDD 4 0 V 2 fsam 0 2 Note 2 s 4 0 V VDD 5 5 V 10 MHz TI50 input frequency fTI5 2 7 V VDD 4 0 V 5 MHz 4...

Page 377: ...J1V0UD 377 TCY vs VDD 5 0 1 0 2 0 0 4 0 2 0 1 Supply voltage VDD V Cycle time T CY s 0 10 0 1 0 2 0 3 0 4 0 5 0 6 0 5 5 2 7 3 3 Guaranteed operation range 20 0 16 0 0 238 0 125 4 17 Remark The values...

Page 378: ...TYP MAX Unit 4 0 V VDD 5 5 V 200 ns 3 3 V VDD 4 0 V 240 ns SCK10 cycle time tKCY1 2 7 V VDD 3 3 V 400 ns SCK10 high low level width tKH1 tKL1 tKCY1 2 10 ns SI10 setup time to SCK10 tSIK1 30 ns SI10 h...

Page 379: ...1V0UD 379 AC Timing Test Points Excluding X1 0 8VDD 0 2VDD Test points 0 8VDD 0 2VDD Clock Timing X1 VIH4 MIN VIL4 MAX 1 fXP tXL tXH TI Timing TI000 TI010 tTIL0 tTIH0 TI50 1 fTI5 tTIL5 tTIH5 Interrupt...

Page 380: ...all error Notes 1 2 2 7 V AVREF 4 0 V 0 3 0 6 FSR 4 0 V AVREF 5 5 V 14 100 s Conversion time tCONV 2 7 V AVREF 4 0 V 17 100 s 4 0 V AVREF 5 5 V 0 4 FSR Zero scale error Notes 1 2 2 7 V AVREF 4 0 V 0 6...

Page 381: ...supply rise time tPTH VDD 0 V 2 1 V 0 0015 ms Response delay time 1 Note tPTHD When power supply rises after reaching detection voltage MAX 3 0 ms Response delay time 2 Note tPD When VDD falls 1 0 ms...

Page 382: ...W 0 2 ms Operation stabilization wait time Note 2 tLWAIT 0 1 0 2 ms Notes 1 Time required from voltage detection to interrupt output or internal reset output 2 Time required from setting LVION to 1 to...

Page 383: ...time Twrwa 500 Note 2 s Number of rewrites per chip Cerwr 1 erase 1 write after erase 1 rewrite Note 3 100 Note 2 Times Notes 1 The prewrite time before erasure and the erase verify time writeback tim...

Page 384: ...OP 7 62 mm 300 A K D E F G H J P 30 16 1 15 A detail of lead end M M T MILLIMETERS 0 65 T P 0 45 MAX 0 13 0 5 6 1 0 2 0 10 9 85 0 15 0 17 0 03 0 1 0 05 0 24 1 3 0 1 8 1 0 2 1 2 0 08 0 07 1 0 0 2 3 5 3...

Page 385: ...ted illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware When accessing the peripheral hardware that may cause a conflict therefore the CPU repeatedly...

Page 386: ...ADS Write PFM Write PFT Write 2 to 5 clocks Note when ADM 5 flag 1 2 to 9 clocks Note when ADM 5 flag 0 ADCR Read 1 to 5 clocks when ADM 5 flag 1 1 to 9 clocks when ADM 5 flag 0 A D converter Calculat...

Page 387: ...3 A D converter Table 25 2 Number of Wait Clocks and Number of Execution Clocks on Occurrence of Wait A D Converter On execution of MOV ADM A MOV ADS A or MOV A ADCR When fX 10 MHz tCPUL 50 ns Value...

Page 388: ...es Unless otherwise specified products supported by IBM PC ATTM compatibles are compatible with PC98 NX series computers When using PC98 NX series computers refer to the explanation for IBM PC AT comp...

Page 389: ...etc In circuit emulatorNote 3 Emulation board Emulation probe Conversion socket or conversion adapter Target system Flash programmer Flash memory write adapter Flash memory Software package Project m...

Page 390: ...robe Conversion socket or conversion adapter Target system Flash programmer Flash memory write adapter Flash memory Software package Project manager Windows only Note 2 Software package Flash memory w...

Page 391: ...te 4 Emulation probe Target system Flash programmer Flash memory write adapter Flash memory Software package Project manager Windows only Note 3 Software package Flash memory write environment Control...

Page 392: ...n to the 78K 0 Series are combined in this package SP78K0 78K 0 Series software package Part number S SP78K0 Remark in the part number differs depending on the host machine and OS used S SP78K0 Host M...

Page 393: ...n using CC78K0 in PC environment This C compiler package is a DOS based application It can also be used in Windows however by using the project manager included in assembler package on Windows CC78K0...

Page 394: ...D FD 3K15 SPARCstation SunOS Rel 4 1 4 Solaris Rel 2 5 1 1 4 inch CGMT A 3 Control Software Project manager This is control software designed to enable efficient user program development in the Window...

Page 395: ...e This is PC card and interface cable required when using a notebook type computer as the host machine PCMCIA socket compatible IE 70000 PC IF C Interface adapter This adapter is required when using a...

Page 396: ...onversion socket connects the NP 30MC to a target system board designed to mount a 30 pin plastic SSOP MC 5A4 type NSPACK30BK Socket for connecting target YSPACK30BK Socket for connecting emulator HSP...

Page 397: ...bugger supports the in circuit emulators for the 78K 0 Series The ID78K0 NS is Windows based software It has improved C compatible debugging functions and can be display the results of tracing with th...

Page 398: ...designing a system Figure B 1 Distance Between In Circuit Emulator and Conversion Adapter 150 mm Emulation board part number pending CN1 Emulation probe NP 30MC Conversion adapter YSPACK30BK NSPACK30B...

Page 399: ...mm 37 mm Emulation probe NP 30MC 13 mm Emulation board part number pending 15 mm 20 mm 5 mm Board on end of NP 30MC Conversion adapter YSPACK30BK NSPACK30BK Guide pin YQ Guide Target system Remarks 1...

Page 400: ...generator control register 6 BRGC6 236 C Capture compare control register 00 CRC00 111 Clock monitor mode register CLM 312 Clock selection register 6 CKSR6 234 E 8 bit timer compare register 50 CR50 1...

Page 401: ...2 77 Port mode register 3 PM3 77 Port register 0 P0 79 Port register 1 P1 79 Port register 12 P12 79 Port register 13 P13 79 Port register 2 P2 79 Port register 3 P3 79 Power fail comparison mode regi...

Page 402: ...0 CR000 106 16 bit timer capture compare register 010 CR010 108 16 bit timer counter 00 TM00 106 16 bit timer mode control register 00 TMC00 109 16 bit timer output control register 00 TOC00 112 T Tim...

Page 403: ...lection register 6 234 CLM Clock monitor mode register 312 CMP00 8 bit timer H compare register 00 158 CMP01 8 bit timer H compare register 01 158 CMP10 8 bit timer H compare register 10 158 CMP11 8 b...

Page 404: ...l comparison mode register 188 PFS Flash status register 352 PFT Power fail comparison threshold register 188 PM0 Port mode register 0 77 114 PM1 Port mode register 1 77 147 162 210 239 267 PM12 Port...

Page 405: ...mode control register 00 109 TMC50 8 bit timer mode control register 50 146 TMHMD0 8 bit timer H mode register 0 159 TMHMD1 8 bit timer H mode register 1 159 TOC00 16 bit timer output control registe...

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