Preliminary User’s Manual U16846EJ1V0UD
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CHAPTER 18 POWER-ON-CLEAR CIRCUIT
18.1 Functions of Power-on-Clear Circuit
The power-on-clear circuit (POC) has the following functions.
•
Generates internal reset signal at power on.
•
Compares supply voltage (V
DD
) and detection voltage (V
POC
= 2.1 V
±
0.1 V
Note
), and generates internal reset
signal when V
DD
< V
POC
.
Note This value may change after evaluation.
Cautions 1. If an internal reset signal is generated in the POC circuit, the reset control flag register
(RESF) is cleared to 00H.
2. The supply voltage is V
DD
= 2.0 to 5.5 V when the Ring-OSC clock or subsystem clock is used,
but be sure to use the product in a voltage range of 2.2 to 5.5 V because the detection voltage
(V
POC
) of the POC circuit is 2.1 V
±
0.1 V.
Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that
indicates the reset cause is located in the reset control flag register (RESF) for when an internal reset
signal is generated by the watchdog timer (WDT), low-voltage-detection (LVI) circuit, or clock monitor.
RESF is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT,
LVI, or the clock monitor.
For details of the RESF, see CHAPTER 16 RESET FUNCTION.
