CHAPTER 19 LOW-VOLTAGE DETECTOR
Preliminary User’s Manual U16846EJ1V0UD
330
Figure 19-6. Example of Software Processing After Release of Reset (1/2)
•
If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage
Yes
LVI
; The
Ring-OSC clock is set as the CPU clock when the reset signal is generated
;
The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
can be identified by the RESF register.
;
Change the CPU clock from the Ring-OSC clock to the high-speed
system clock.
;
Check the stabilization of oscillation of the high-speed system clock
by using the OSTC register
Note 3
.
;
TMIFH1 = 1: Interrupt request is generated.
;
Initialization of ports
;
8-bit timer H1 can operate with the Ring-OSC clock.
Source: f
R
(480 kHz (MAX.))/2
7
×
compare value 200 = 53 ms
(f
R
: Ring-OSC clock oscillation frequency)
No
Note 1
Reset
Checking cause
of reset
Note 2
Check stabilization
of oscillation
Change CPU clock
50 ms has passed?
(TMIFH1 = 1?)
Initialization
processing
Start timer
(set to 50 ms)
Notes 1. If reset is generated again during this period, initialization processing is not started.
2. A flowchart is shown on the next page.
3. Waiting for the oscillation stabilization time is not required when the external RC oscillation clock is
selected as the high-speed system clock by the option byte. Therefore, the CPU clock can be
switched without reading the OSTC value.
