CHAPTER 15 STANDBY FUNCTION
Preliminary User’s Manual U16846EJ1V0UD
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(1) HALT
mode
HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. If
the high-speed system clock and Ring-OSC clock oscillator are operating before the HALT mode is set,
oscillation of the high-speed system clock and Ring-OSC clock continues. In this mode, operating current is not
decreased as much as in the STOP mode. However, the HALT mode is effective for restarting operation
immediately upon interrupt request generation and carrying out intermittent operations.
(2) STOP
mode
STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator
stops, stopping the whole system, thereby considerably reducing the CPU operating current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is
released, select the HALT mode if it is necessary to start processing immediately upon interrupt request
generation.
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is
set are held. The I/O port output latches and output buffer statuses are also held.
Cautions 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before
executing STOP instruction.
2. The following sequence is recommended for operating current reduction of the A/D converter
when the standby function is used: First clear bit 7 (ADCS) of the A/D converter mode
register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP
instruction.
3. If the Ring-OSC oscillator is operating before the STOP mode is set, oscillation of the Ring-
OSC clock cannot be stopped in the STOP mode. However, when the Ring-OSC clock is used
as the CPU clock, operation is stopped for 17/f
R
(s) after STOP mode is released.
