Preliminary User’s Manual U16846EJ1V0UD
9
CONTENTS
CHAPTER 1 OUTLINE ............................................................................................................................ 15
1.1 Features ...................................................................................................................................... 15
1.2 Applications................................................................................................................................ 16
1.3 Ordering
Information ................................................................................................................. 16
1.4 Pin Configuration (Top View).................................................................................................... 17
1.5 K1 Family Lineup ....................................................................................................................... 18
1.5.1 78K0/Kx1,
78K0/Kx1+ product lineup ..............................................................................................18
1.5.2 V850ES/Kx1,
V850ES/Kx1+ product lineup .....................................................................................21
1.6 Block
Diagram ............................................................................................................................ 24
1.7 Outline of Functions .................................................................................................................. 25
CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 27
2.1 Pin Function List ........................................................................................................................ 27
2.2 Description of Pin Functions .................................................................................................... 29
2.2.1 P00
to
P03 (port 0)...........................................................................................................................29
2.2.2 P10
to
P17 (port 1)...........................................................................................................................29
2.2.3 P20
to
P23 (port 2)...........................................................................................................................30
2.2.4 P30
to
P33 (port 3)...........................................................................................................................30
2.2.5 P120
(port 12) ..................................................................................................................................30
2.2.6 P130
(port 13) ..................................................................................................................................31
2.2.7 AV
REF
..............................................................................................................................................31
2.2.8 AV
SS
................................................................................................................................................31
2.2.9 RESET .............................................................................................................................................31
2.2.10 X1 and X2 ........................................................................................................................................31
2.2.11 CL1 and CL2 ....................................................................................................................................31
2.2.12 V
DD
..................................................................................................................................................31
2.2.13 V
SS
..................................................................................................................................................31
2.2.14 FLMD0 and FLMD1..........................................................................................................................31
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins......................................... 32
CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 34
3.1 Memory
Space............................................................................................................................ 34
3.1.1 Internal
program memory space ......................................................................................................38
3.1.2 Internal
data memory space.............................................................................................................39
3.1.3 Special
function
register (SFR) area ................................................................................................39
3.1.4 Data
memory addressing .................................................................................................................40
3.2 Processor
Registers .................................................................................................................. 43
3.2.1 Control
registers...............................................................................................................................43
3.2.2 General-purpose registers ...............................................................................................................47
3.2.3 Special
Function Registers (SFRs) ..................................................................................................48
3.3 Instruction Address Addressing .............................................................................................. 52
3.3.1 Relative addressing..........................................................................................................................52
3.3.2 Immediate addressing......................................................................................................................53
3.3.3 Table
indirect addressing .................................................................................................................54
3.3.4 Register addressing .........................................................................................................................54
