Preliminary User’s Manual U16846EJ1V0UD
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CHAPTER 16 RESET FUNCTION
The following five operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by clock monitor high-speed system clock oscillation stop detection
(4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)
External and internal resets have no functional differences. In both cases, program execution starts at the address
at 0000H and 0001H when the reset signal is input.
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, high-speed system
clock oscillation stop is detected by the clock monitor, or by POC and LVI circuit voltage detection, and each item of
hardware is set to the status shown in Table 16-1. Each pin is high impedance during reset input or during the
oscillation stabilization time just after reset release, except for P130, which is low-level output.
When a high level is input to the RESET pin, the reset is released and program execution starts using the Ring-
OSC clock after the CPU clock operation has stopped for 17/f
R
(s). A reset generated by the watchdog timer and
clock monitor sources is automatically released after the reset, and program execution starts using the Ring-OSC
clock after the CPU clock operation has stopped for 17/f
R
(s) (see Figures 16-2 to 16-4). Reset by POC and LVI
circuit power supply detection is automatically released when V
DD
> V
POC
or V
DD
> V
LVI
after the reset, and program
execution starts using the Ring-OSC clock after the CPU clock operation has stopped for 17/f
R
(s) (see CHAPTER 18
POWER-ON-CLEAR CIRCUIT and CHAPTER 19 LOW-VOLTAGE DETECTOR).
Cautions 1. For an external reset, input a low level for 10
µ
s or more to the RESET pin.
2. During reset input, the high-speed system clock and Ring-OSC clock stop oscillating.
3. When the STOP mode is released by a reset, the STOP mode contents are held during reset
input. However, the port pins become high-impedance, except for P130, which is set to low-
level output.
