NEC 78K0/KB1+, Preliminary User'S Manual

Page: 363 / 405

CHAPTER 22 INSTRUCTION SET
Preliminary User’s Manual U16846EJ1V0UD
363
Clocks Flag
Instruction
Group
Mnemonic Operands Bytes
Note 1 Note 2
Operation
Z AC CY
A, #byte 2 4
−
A
←
A
∨
byte
×
saddr, #byte 3 6 8 (saddr)
←
(saddr)
∨
byte
×
A, r
Note 3
2 4
−
A
←
A
∨
r
×
r, A 2 4
−
r
←
r
∨
A
×
A, saddr 2 4 5 A
←
A
∨
(saddr)
×
A, !addr16 3 8 9 + n A
←
A
∨
(addr16)
×
A, [HL] 1 4 5 + n A
←
A
∨
(HL)
×
A, [HL + byte] 2 8 9 + n A
←
A
∨
(HL + byte)
×
A, [HL + B] 2 8 9 + n A
←
A
∨
(HL + B)
×
OR
A, [HL + C] 2 8 9 + n A
←
A
∨
(HL + C)
×
A, #byte 2 4
−
A
←
A
∨
byte
×
saddr, #byte 3 6 8 (saddr)
←
(saddr)
∨
byte
×
A, r
Note 3
2 4
−
A
←
A
∨
r
×
r, A 2 4
−
r
←
r
∨
A
×
A, saddr 2 4 5 A
←
A
∨
(saddr)
×
A, !addr16 3 8 9 + n A
←
A
∨
(addr16)
×
A, [HL] 1 4 5 + n A
←
A
∨
(HL)
×
A, [HL + byte] 2 8 9 + n A
←
A
∨
(HL + byte)
×
A, [HL + B] 2 8 9 + n A
←
A
∨
(HL + B)
×
XOR
A, [HL + C] 2 8 9 + n A
←
A
∨
(HL + C)
×
A, #byte 2 4
−
A
−
byte
× × ×
saddr, #byte 3 6 8 (saddr)
−
byte
× × ×
A, r
Note 3
2 4
−
A
−
r
× × ×
r, A 2 4
−
r
−
A
× × ×
A, saddr 2 4 5 A
−
(saddr)
× × ×
A, !addr16 3 8 9 + n A
−
(addr16)
× × ×
A, [HL] 1 4 5 + n A
−
(HL)
× × ×
A, [HL + byte] 2 8 9 + n A
−
(HL + byte)
× × ×
A, [HL + B] 2 8 9 + n A
−
(HL + B)
× × ×
8-bit
operation
CMP
A, [HL + C] 2 8 9 + n A
−
(HL + C)
× × ×
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.