CHAPTER 5 CLOCK GENERATOR
Preliminary User’s Manual U16846EJ1V0UD
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(4) Main OSC control register (MOC)
This register selects the operation mode of the high-speed system clock.
This register is used to stop the high-speed system clock oscillator operation when the CPU is operating with the
Ring-OSC clock. Therefore, this register is valid only when the CPU is operating with the Ring-OSC clock.
MOC can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-5. Format of Main OSC Control Register (MOC)
Address: FFA2H After reset: 00H R/W
Symbol
<7>
6 5 4 3 2 1 0
MOC
MSTOP
0 0 0 0 0 0 0
MSTOP
Control of high-speed system clock oscillator operation
0
High-speed system clock oscillator operating
1
High-speed system clock oscillator stopped
Caution Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before setting
MSTOP.
(5) Oscillation stabilization time counter status register (OSTC)
This is the status register of the high-speed system clock oscillation stabilization time counter. If the Ring-OSC
clock is used as the CPU clock, the high-speed system clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction,
MSTOP = 1 clear OSTC to 00H.
Caution Waiting for the oscillation stabilization time is not required when the external RC oscillation
clock is selected as the high-speed system clock by the option byte. Therefore, the CPU clock
can be switched without reading the OSTC value.
