CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16846EJ1V0UD
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(6) Operation of OVF00 flag
<1> The OVF00 flag is also set to 1 in the following case.
When of the following modes: the mode in which clear & start occurs on a match between TM00 and
CR000, the mode in which clear & start occurs at the TI000 pin valid edge, or the free-running mode, is
selected
↓
CR000 is set to FFFFH
↓
TM00 is counted up from FFFFH to 0000H.
Figure 6-36. Operation Timing of OVF00 Flag
Count clock
CR000
TM00
OVF00
INTTM000
FFFFH
FFFEH
FFFFH
0000H
0001H
<2> Even if the OVF00 flag is cleared before the next count clock (before TM00 becomes 0001H) after the
occurrence of TM00 overflow, the OVF00 flag is re-set newly and clear is disabled.
(7) Conflicting
operations
Conflict between the read period of the 16-bit timer capture/compare register (CR000/CR010) and capture trigger
input (CR000/CR010 used as capture register)
Capture trigger input has priority. The data read from CR000/CR010 is undefined.
Figure 6-37. Capture Register Data Retention Timing
Count clock
TM00 count value
Edge input
INTTM010
Capture read signal
CR010 capture value
N
N + 1
N + 2
M
M + 1
M + 2
X
N + 2
Capture, but
read value is
not guaranteed
Capture
M + 1
