CHAPTER 5 CLOCK GENERATOR
Preliminary User’s Manual U16846EJ1V0UD
83
Figure 5-1. Block Diagram of Clock Generator
X1[CL1]
X2[CL2]
High-speed
system clock
oscillator
f
XP
f
X
2
2
Internal bus
Ring-OSC mode
register (RCM)
STOP
MSTOP
Main OSC
control register
(MOC)
f
X
2
3
f
X
2
4
f
X
2
3
Internal bus
Ring-OSC
oscillator
Option byte (RINGOSC)
1: Cannot be stopped
0. Can be stopped
RSTOP
Controller
PCC1 PCC0
Control
signal
CPU
clock
(f
CPU
)
f
CPU
Processor clock
control register
(PCC)
PCC2
MCM0
MCS
Main clock
mode register
(MCM)
OSTS1 OSTS0
OSTS2
Oscillation stabilization
time counter
Oscillation
stabilization time
select register
(OSTS)
3
MOST
16
MOST
15
MOST
14
MOST
13
MOST
11
Oscillation
stabilization
time counter
status register
(OSTC)
f
R
Clock to peripheral
hardware
Prescaler
Operation
clock switch
f
X
8-bit timer H1,
watchdog timer
Prescaler
Prescaler
Selector
C
P
U
Crystal/ceramic
oscillator
Note
External RC
oscillator
Note
Note Select one of these as the high-speed system clock oscillator by the option byte.
