CHAPTER 11 SERIAL INTERFACE UART0 (
µ
PD78F0102H AND 78F0103H ONLY)
Preliminary User’s Manual U16846EJ1V0UD
208
(2) Asynchronous serial interface reception error status register 0 (ASIS0)
This register indicates an error status on completion of reception by serial interface UART0. It includes three
error flag bits (PE0, FE0, OVE0).
This register is read-only by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0. 00H is read when this
register is read.
Figure 11-3. Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0)
Address: FF73H After reset: 00H R
Symbol
7 6 5 4 3 2 1 0
ASIS0
0 0 0 0 0
PE0
FE0
OVE0
PE0
Status flag indicating parity error
0
If POWER0 = 0 and RXE0 = 0, or if the ASIS0 register is read.
1
If the parity of transmit data does not match the parity bit on completion of reception.
FE0
Status flag indicating framing error
0
If POWER0 = 0 and RXE0 = 0, or if the ASIS0 register is read.
1
If the stop bit is not detected on completion of reception.
OVE0
Status flag indicating overrun error
0
If POWER0 = 0 and RXE0 = 0, or if the ASIS0 register is read.
1
If receive data is set to the RXB register and the next reception operation is completed before the
data is read.
Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of
asynchronous serial interface operation mode register 0 (ASIM0).
2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of
stop bits.
3. If an overrun error occurs, the next receive data is not written to receive buffer register 0
(RXB0) but discarded.
4. If data is read from ASIS0, a wait cycle is generated. For details, see CHAPTER 25 CAUTIONS
FOR WAIT.
