Platinum™ IP3
Installation and Operation Manual
Frame Synchronizer and Demultiplexing Input Modules (PT-FSDMX-IBG/PT-FSDMXO-IBG, PT-FSDX8C1D-IBG, PT-FSDMX8O1D-IBG)
© 2016 Imagine Communications Corp.
Proprietary and Confidential.
September 2016 | Page 160
LED Indicators
Figure 69:
PT-FSDMX Card-Edge LED Indicators
Table 77:
PT-FSDMX-IBG/PT-FSDMXO-IBG Specific LEDs
LED
Function
Channel Status
Ch (1 - 8)
Red: Power on test failed
FPGA Temp
FPGA Temp (A - B)
Red: Above temperature limit
Power-Up sequence
Due to the complexity of the board and its parameter list, it takes about 2.5 minutes after power-cycling
a board before it is fully operational.
About 30 seconds after power-cycling, a board is ready to detect input signals, but it outputs a 75% color
bar test pattern of the same video standard as the detected input signal until the PT-Resource card has
completed uploading the previously used configuration (parameters).
