Delta VFD-ED Series, User Manual

Page: 122 / 389

Ch07 Option Cards | VFD-ED
7-17
DATA+(DATA),
DATA-(/DATA)
RS-485 communication
interface
Terminal resistance is about 130
Ω
.
CLOCK+, CLOCK-
CLOCK differential output
for ENDAT
Line driver RS422 level output
NOTE
.

Verify that the SW2 switch is set to the correct output voltage before powering on.

Keep the motor drive wiring away from any high voltage lines to avoid interference.
Wiring Diagram
Set the Frequency Division Signal
①
After the encoder inputs a PULSE signal, there is an output signal by the division factor “n.” Set the value
in Pr.10-29 (PG card’s frequency division output).
②
Set Pr.10-29 (PG card’s frequency division output):
The decimal frequency division output setting; range of the division factor “n”: 1–31.
③
Pr.10-30 (PG card’s frequency division output mode)
Bit3 Bit2 Bit1 Bit0
X X OUT/M IN/M
OUT/M: Pulse output mode for frequency division;
IN/M: Pulse input mode for frequency division;
“X” is for backup while “0” is a value to write.