All data values in the sync packet must be available before they are
fetched from the internal FPGA memory. The sync packet is transmitted
over the backplane to the MCU. Every drive module has a dedicated
communication channel with the MCU, so the sync packets of all drive
modules in the node are transmitted at the same time in parallel to the
MCU.
●
Data availability for Current Control Loop (CCL) calculation.
The CCL requires position data and current data for the current control
algorithm. The data must be available before the CCL is triggered.
●
Data availability for Position Velocity Loop (PVL) calculation.
The PVL requires the actual position data available on the latch
moment. The latch moment depends on the PVL frequency.
As all activities are derived from a network-synchronized clock, all activities in
each NYCe 4000 node are executed synchronously.
Sample time definitions
All activities, such as start of the A/D conversion or latch moment of encoder
data, start of the PVL calculation and transmission of the sync packet, are
derived from a single clock source on the MCU. The sync packet is
transmitted from the drive module to the MCU once every MCU sample.
SinCos
PVL (on drive)
ADC
digital encoder
digital I/O
Quadrature
sync
latch
MCU sample
latch
latch
latch
32 kHz (31.25 µs)
latch
MCU sample
MCU sample (node) frequency 8 kHz (125 µs)
PVL (on drive)
PVL (on drive)
PVL (on drive)
sync
(Note 1)
(Note 2)
Fig. 13-2:
Relation of MCU sample, PVL sample and encoder data (PVL on
drive @ 32 kHz)
fig. 13-2 "Relation of MCU sample, PVL sample and encoder data (PVL on
shows that the information of the analog to
digital conversion is not available in time to be included in the sync packet
(Note 1). For this reason, the sync packet always contains the analog value
of the previous PVL sample.
fig. 13-2 "Relation of MCU sample, PVL sample
and encoder data (PVL on drive @ 32 kHz)" on page 160
information of a digital encoder will not be available in time for the PVL (on
the drive module) when the PVL frequency is set at 32 kHz (Note 2). For this
reason, the PVL frequency must be set lower if you use a digital encoder, see
the following subchapter "Encoder position data". At the lower PVL frequency
the PVL (on the drive module) can use the actual information of the digital
encoder, see
fig. 13-3 "Relation of MCU sample, PVL sample and encoder
data (PVL on drive @ 16 kHz)" on page 161
. However, the sync packet
always contains the information of the digital encoder of the previous PVL
sample.
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Encoders
NYCe 4000 Multi-axis motion control system Hardware Sys‐
tem Manual
Bosch Rexroth AG R911337671_Edition 18
