Appendix A
Connector Pinouts
A-17
A.1.2.8
CompactPCI J2/P2 Signal Descriptions
Caution –
Select VIO pins
must
be set to 5V, and
not
to universal.
A.1.2.9
CompactPCI J3/P3 Connector Pinouts
TABLE A-11
lists the CompactPCI J3 connector pin assignments.
9
GND
CPCI_AD[52]
GND
VIO
1
(+EP_5V)
CPCI_AD[51]
CPCI_AD[50]
GND
8
GND
CPCI_AD[56]
CPCI_AD[55]
CPCI_AD[54]
GND
CPCI_AD[53]
GND
7
GND
CPCI_AD[59]
GND
VIO
*
(+EP_5V)
CPCI_AD[58]
CPCI_AD[57]
GND
6
GND
CPCI_AD[63]
CPCI_AD[62]
CPCI_AD[61]
GND
CPCI_AD[60]
GND
5
GND
CPCI_C/BE[5]#
CPCI_64_EN#
VIO
*
(+EP_5V)
CPCI_C/BE[4]#
CPCI_PAR64
GND
4
GND
rsv
BRSVP
CPCI_C/BE[7]#
GND
CPCI_C/BE[6]#
GND
3
GND
CPCI_CLK4
GND
CPCI_GNT3#
CPCI_REQ4#
CPCI_GNT4#
GND
2
GND
CPCI_CLK2
CPCI_CLK3
CPCI_SYSEN#
CPCI_GNT2#
CPCI_REQ3#
GND
1
GND
CPCI_CLK1
GND
CPCI_REQ1#
CPCI_GNT1#
CPCI_REQ2#
GND
1
Caution –
Select VIO pins
must
be 5V, and
not
universal.
TABLE A-10
CompactPCI J2/P2 Signal Descriptions
Signal Name
Description
CPCI_GA[4..0]
Geographical Address. Signals for unique slot identification.
BRSVP
Bused reserve pins.
PRST#
Backplane button reset input to SMC.
DEG#, FAL#
Power subsystem status signals input to SMC.
CPCI_64_EN#
PICMG hot-swap spec 2.1 R1.0 signal; designates 64-bit capability of backplane slot.
CPCI_PAR64
cPCI parity 64 bit; calculated across AD[63..32] and C/ BE[7..4]#.
CPCI_SYSEN#
System slot identification, grounded on the cPCI system slot.
TABLE A-9
CompactPCI J2/P2 Connector Pin Assignments
(Continued)
Pin
Row Z
Row A
Row B
Row C
Row D
Row E
Row F
Содержание Netra CT 410
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