Samsung SC32442B54, Руководство пользователя

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K5D2G13ACM-D075
Revision 1.0
December 2006
76
MCP MEMORY
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
CS
RAS
CAS
BA1
A10/AP
CL=3
ADDR
WE
: Don’t care
CLOCK
Page Read & Write Cycle at Same Bank @Burst Length=4, tRDL=2CLK
HIGH
Ra Ca
Ra
CL=2
Row Active Read Write Precharge
Note:
1) To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention.
2) Row precharge will interrupt writing. Last data input, t
RDL
before Row precharge, will be written.
3) DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row pre
charge cycle will be masked internally.
4) t
DAL
, last data in to active delay, is t
RDL
+ t
RP
.
BA0
DQ
t
RDL
Note 3)
(A-Bank) (A-Bank) (A-Bank) (A-Bank)
{
Note 2)
Cb
t
DAL
Note 4)
Note 1)
t
CDL
Read
(A-Bank)
Write
(A-Bank)
Row Active
(A-Bank)
Cc Cd Rb
Rb
Qa1 Dd0 Qa0 Qb0 Dd1 Qb1 Qb2 Dc0 Dc1
Qa1 Dd0 Qa0 Qb0 Dd1 Qb1 Dc0 Dc1
t
RCD
CL=3
CL=2
DQM
{
Note 3) Note 1)
Hi-Z
Hi-Z