Samsung SC32442B54, Руководство пользователя

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K5D2G13ACM-D075
Revision 1.0
December 2006
67
MCP MEMORY
12. About Burst Type Control
Basic
MODE
Sequential Counting
At MRS A
3
= "0". See the BURST SEQUENCE TABLE. (BL=4, 8)
BL=1, 2, 4, 8 and full page.
Interleave Counting
At MRS A
3
= "1". See the BURST SEQUENCE TABLE. (BL=4, 8)
At BL=1, 2 Interleave Counting = Sequential Counting. BL=1, 2, 4, 8 and full page.
Random
MODE
Random column Access
t
CCD
= 1 CLK
Every cycle Read/Write Command with random column address can realize Random
Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
13. About Burst Length Control
Basic
MODE
1
At MRS A
2,1,0
= "000".
At auto precharge, t
RAS
should not be violated.
2
At MRS A
2,1,0
= "001".
At auto precharge, t
RAS
should not be violated.
4 At MRS A
2,1,0
= "010".
8 At MRS A
2,1,0
= "011".
Full Page
At MRS A
2,1,0
= "111".
Wrap around mode(infinite burst length) should be stopped by burst stop.
RAS interrupt or CAS interrupt.
Special
MODE
BRSW
At MRS A
9
= "1".
Read burst =1, 2, 4, 8, full page write Burst =1.
At auto precharge of write, t
RAS
should not be violated.
Random
MODE
Burst Stop
t
BDL
= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively
Using burst stop command, any burst length control is possible.
Interrupt
MODE
RAS Interrupt
(Interrupted by Precharge)
Before the end of burst, Row precharge command of the same bank stops read/write
burst with Row precharge.
t
RDL
= 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
CAS Interrupt
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.